IDT89HPES4T4G2ZCALG8 IDT, Integrated Device Technology Inc, IDT89HPES4T4G2ZCALG8 Datasheet - Page 2

• Manufacturer Part Number: IDT89HPES4T4G2ZCALG8
• Description: IC PCI SW 4LANE 4PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES4T4G2ZCALG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES4T4G2ZCALG8

Product Description
the most efficient high-performance I/O connectivity device for applica-
tions requiring high throughput, low latency and simple board layout. It
provides PCI Express connectivity across 4 lanes and 4 ports. Each
lane provides 5 Gbps of bandwidth in both directions and is fully
compliant with PCI Express Base specification 2.0.
ture. The PCI Express layer consists of SerDes, Physical, Data Link and
Transaction layers in compliance with PCI Express Base specification
Revision 2.0. The PES4T4G2 can operate either as a store and forward
or cut-through switch and is designed to switch memory and I/O transac-
tions. It supports eight Traffic Classes (TCs) and one Virtual Channel
(VC) with sophisticated resource management to enable efficient
switching and I/O connectivity for servers, storage, and embedded
processors with limited connectivity.
IDT 89HPES4T4G2 Data Sheet
Utilizing standard PCI Express interconnect the PES4T4G2 provides
The PES4T4G2 is based on a flexible and efficient layered architec-
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Packaged in a 19mm x 19mm, 324-ball BGA with 1mm ball
spacing
– Support for PCI Express Active State Power Management
– Supports PCI Express Power Budgeting Capability
– Configurable SerDes power consumption
– Unused SerDes are disabled
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
– Each pin may be individually configured as an input or output
– Each pin may be individually configured as an interrupt input
– Some pins have selectable alternate functions
Testability and Debug Features
General Purpose Input/Output Pins
• Supports device power management states: D0, D3
• Supports link power management states: L0, L0s, L1, L2/L3
• Supports optional PCI-Express SerDes Transmit Low-Swing
• Supports numerous SerDes Transmit Voltage Margin
(ASPM) link state
D3
Ready and L3
Voltage Mode
settings
cold
hot
and
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SMBus Interface
provides full access to the configuration registers in the PES4T4G2,
allowing every configuration register in the device to be read or written
by an external agent. The master interface allows the default configura-
tion register values of the PES4T4G2 to be overridden following a reset
with values programmed in an external serial EEPROM. The master
interface is also used by an external Hot-Plug I/O expander.
consist of an SMBus clock pin and an SMBus data pin. The Master
SMBus address is hardwired to 0x50, and the slave SMBus address is
hardwired to 0x77.
in a unified or split configuration. In the unified configuration, shown in
Figure 3(a), the master and slave SMBuses are tied together and the
PES4T4G2 acts both as a SMBus master as well as a SMBus slave on
this bus. This requires that the SMBus master or processor that has
access to PES4T4G2 registers supports SMBus arbitration. In some
systems, this SMBus master interface may be implemented using
general purpose I/O pins on a processor or micro controller, and may
not support SMBus arbitration. To support these systems, the
PES4T4G2 may be configured to operate in a split configuration as
shown in Figure 3(b).
two independent buses and thus multi-master arbitration is never
required. The PES4T4G2 supports reading and writing of the serial
EEPROM on the master SMBus via the slave SMBus, allowing in
system programming of the serial EEPROM.
The PES4T4G2 contains two SMBus interfaces. The slave interface
Two pins make up each of the two SMBus interfaces. These pins
As shown in Figure 3, the master and slave SMBuses may be used
In the split configuration, the master and slave SMBuses operate as
PCI Express
Figure 2 I/O Expansion Application
Slot
Processor
x1
PES4T4G2
x1
4xGbE
I/O
x1
Bridge
North
Processor
4xGbE
I/O
x1
SATA
September 13, 2010
I/O
Memory
Memory
Memory
Memory
SATA
I/O