IDT89HPES4T4G2ZCALG8 IDT, Integrated Device Technology Inc, IDT89HPES4T4G2ZCALG8 Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES4T4G2ZCALG8
• Description: IC PCI SW 4LANE 4PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES4T4G2ZCALG8

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES4T4G2ZCALG8

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES4T4G2 Data Sheet
The following tables list the functions of the pins provided on the PES4T4G2. Some of the functions listed may be multiplexed onto the same pin.
PEREFCLKP
PEREFCLKN
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
PE0RP[0]
PE0RN[0]
PE0TN[0]
PE1RP[0]
PE1RN[0]
PE1TN[0]
PE2RP[0]
PE2RN[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TN[0]
PE0TP[0]
PE1TP[0]
PE2TP[0]
PE3TP[0]
Signal
Signal
Type
Type
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pair for port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is set at 100MHz.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus which operates at 400 KHz.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus which operates at 400 KHz.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 1 PCI Express Interface Pins
Table 2 SMBus Interface Pins
4 of 29
Name/Description
Name/Description
September 13, 2010