IDT89HPES3T3ZBNQG IDT, Integrated Device Technology Inc, IDT89HPES3T3ZBNQG Datasheet - Page 3

• Manufacturer Part Number: IDT89HPES3T3ZBNQG
• Description: IC PCI SW 3LANE 3PORT 132-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES3T3ZBNQG

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 89HPES3T3ZBNQG

General Purpose Input/Output
be configured independently as an input or output through software control, and each GPIO pin is shared with another on-chip function. These alter-
nate functions may be enabled via software or serial configuration EEPROM.
Pin Description
active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low) level.
All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES3T3 Data Sheet
The PES3T3 provides 5 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin may
The following tables lists the functions of the pins provided on the PES3T3. Some of the functions listed may be multiplexed onto the same pin. The
PEREFCLKP
PEREFCLKN
MSMBCLK
MSMBDAT
PE0RP[0]
PE0RN[0]
PE0TN[0]
PE2RP[0]
PE2RN[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TN[0]
PE0TP[0]
PE2TP[0]
PE3TP[0]
Signal
Signal
Type
Type
I/O
I/O
O
O
O
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pair for port 0.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 0.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is 100 MHz.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus.
Table 1 PCI Express Interface Pins
Table 2 SMBus Interface Pins
3 of 31
Name/Description
Name/Description
October 8, 2010