IDT77V550S25DT8 IDT, Integrated Device Technology Inc, IDT77V550S25DT8 Datasheet - Page 10

• Manufacturer Part Number: IDT77V550S25DT8
• Description: IC SW MEMORY 8X8 1.2BGPS 80-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V550S25DT8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V550S25DT8

Manager writes and reads the data registers one at a time. On the first write or read register zero is chosen. With each subsequent write or read cycle
successively higher numbered registers are selected. Figure 9 gives a typical Read sequence across the manager bus; Figure 10 illustrates a Write
operation. Note the need for the acknowledgment before proceeding.
available in the SwitchStar User's Manual, Section 3.
Manager Bus Read Timing Waveform
Manager Bus Read Timing Waveform
Manager Bus Write Timing Waveform
Manager Bus Write Timing Waveform
Note: 1. Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is
Note: 1. Write operations, both for Commands and Data, are synchronous to the rising edge of MSTRB. The data placed on the MDATA pins is
IDT77V550
For the IDT77V500 commands available, refer to the IDT77V500 Switch Controller Manager Bus Command Table. Additional command details are
MSTRB
M STRB
MDATA
MDATA
MR/
MR/
MD/
MD/
determined by the state of the MD/C pin.
2. The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. That is, data is
available to be read one asynchronous tAMD time after the falling edge of MSTRB if MR/W is HIGH.
3. After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the
IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been
acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the
4. A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
5. Waveform illustrates first two bytes of data only. Additional bytes may be available based on command used.
6.The tHMRW delay time is guaranteed by design to be two SCLK cycles in duration. The tHM delay time is guaranteed by design to be
between two and four clocks in duration.
2. Either a Read cycle was completed or a Status Acknowledge was executed immediately prior to the first MSTRB of this write waveform.
3. The combination of MSTRB Low and MR/W High (Read mode) asynchronously enables the MDATA pins as outputs. The data placed on
the MDATA pins is determined by the state of the MD/C pin.
4. After the Command is written, the Manager must take MR/W High (Read mode) to wait for a valid Command Acknowledge from the
acknowledged by the IDT77V500. This may take multiple IDT77V500 SCLK cycles based on possible higher priority operations that the
IDT77V500 must support.
5. A valid Acknowledge from the IDT77V500 is indicated by a High Command Acknowledge bit (Bit 7 of the Status Register).
6.The tHMRW and tHMD delay times are guaranteed by design to be two SCLK cycles in duration. The tHM delay time is guaranteed by design to be
between two and four clocks in duration.
IDT77V500 must support.
determined by the state of the MD/C pin.
IDT77V500 before proceeding. Reading a High Bit 7 of the status register under these conditions indicates the command has been
W
W
C
C
(2)
8 ADDR bits
t
SMRW
t
ADDR
Write first
SMD
t
SM
Write Data Byte 0
t
SMRW
t
SMD
t
DATA
SM
IN
t
t
HM
HMD
t
MCH
t
T0
t
t
IN
HMRW
t
HM
HMRW
HMD
t
MCYC
t
MCL
8 ADDR bits
ADDR
Write last
Write Data Byte 12
IN
DATA
T12
IN
t
MCH
t
MCYC
Read Command
t
SMRW
Write Cycle-
t
CMD
t
MCL
SM
Figure 10 Manager Bus Write Timing Waveform
Figure 9 Manager Bus Read Timing Waveform
IN
Write Command
t
SMRW
Write Cycle-
t
CMD
SM
IN
Acknowledge Read
(2)
t
AMD
Acknowledge Read
(3)
t
AMD
DATA
10 of 19
OUT
t
OHMD
DATA
(1)
(1)
(1)
(1)
Acknowledge Read
OUT
(3)
t
OHMD
Acknowledge Read
DATA
OUT
Valid Command Acknowledge
DATA
Acknowledge Read –
OUT
Acknowledge Read
DATA
(4)
OUT
(4)
DATA
t
AMD
OUT
Read Byte 0
Valid Command Acknowledge
Acknowledge Read –
DATA
OUT
t
OHMD
DATA
Read Byte 1
OUT
(5)
June 22, 2001
DATA
OUT
(5)
4523 drw 10
4523 drw 09