IDT77V550S25DT8 IDT, Integrated Device Technology Inc, IDT77V550S25DT8 Datasheet - Page 8

• Manufacturer Part Number: IDT77V550S25DT8
• Description: IC SW MEMORY 8X8 1.2BGPS 80-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT77V550S25DT8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 77V550S25DT8

DPI Transmit Path
DPI Transmit Path
Manager. It has 4-bit input data buses (OPD[3:0] and OPD
cation. Other signals associated with this interface are DPI Transmit Start of Frame (OFRM and OFRM
OCLK
first valid nibble of data.
IDATA/IDATA
IDATA/IDATA
ODATA/ODATA
ODATA/ODATA
IDT77V550
The DPI Transmit Path is used to transfer cells from the IDT77V400 Switching Memory or other DPI device to and through the IDT77V550 Switch
OCLK is an input to the Switch Manager, and OCLK
OFRM/OFRM
Figure 7 and Figure 8 illustrate these timing relationships for a signal cell transfer and a Back-to-Back cell transfer on the transmit DPI bus.
IFRM/IFRM
IFRM/IFRM
M
OFRM/OFRM
OFRM/OFRM
ICLK/ICLK
ICLK/ICLK
OCLK/OCLK
OCLK/OCLK
).
M
M
[3:0]
[3:0]
M
M
M
[3:0]
[3:0]
M
M
M
M
M
M
M
M
is the start of frame marker. This signal is one OCLK/OCLK
105
105
0
0
1
1
Figure 8 Back-to-Back Cell Transfer on Transmit DPI Bus
Figure 6 Back-to-Back Cell Transfer on Receive DPI Bus
2
Figure 7 One Cell Transfer on Transmit DPI Bus
Figure 5 One Cell Transfer on Receive DPI Bus
2
M
to the IDT77V400 Switching Memory (an output) is generated from OCLK.
0
M
[3:0]) and follows the standard DPI timing characteristics as described in the DPI specifi-
0
1
8 of 19
1
2
M
2
cycle long and is asserted high one OCLK/OCLK
104
104
104
104
105
M
), and DPI Transmit Clock (OCLK and
105
105
105
0
0
1
M
June 22, 2001
1
cycle before the
2
4523 drw 06
4523 drw 05
2
4523 drw 08
4523 drw 07