IDT72V51353L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51353L7-5BB8 Datasheet - Page 10

• Manufacturer Part Number: IDT72V51353L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51353L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51353L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 44-48 and Figures 27-29.
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
TMS
TRST
WADEN
WCLK
WEN
WRADD
[5:0]
V
GND
Symbol
CC
(2)
(2)
Write Address Enable
Write Clock
Write Enable
Write Address Bus
+3.3V Supply
Ground Pin
JTAG Mode Select
JTAG Reset
Name
I/O TYPE
Ground
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
INPUT
LVTTL
Power
TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
Din. The queue to be written to is selected via the WRADD address bus and a rising edge of WCLK while
to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless of the
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part
has been completed and SENO has gone LOW.
When enabled by WEN, the rising edge of WCLK writes data into the selected queue via the input bus,
WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also select the device
to be placed on the PAFn bus during direct flag operation. During polled flag operation the PAFn bus is
cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK. The PAFn, PAF and FF
outputs are all synchronized to WCLK. During device expansion the FXO and FXI signals are based on
WCLK. The WCLK must be continuous and free-running.
The WEN input enables write operations to a selected queue based on a rising edge of WCLK. A queue
state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK cycle
after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn bus (in
polled mode) or to select the device , (in direct mode).
For the 8Q device the WRADD bus is 6 bits. The WRADD bus is a dual purpose address bus. The first
function of WRADD is to select a queue to be written to. The least significant 3 bits of the bus, WRADD[2:0]
are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits,
WRADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. These 3 MSB’s will address a device with the matching ID code. The address present on the WRADD
bus will be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data present on
the Din bus can be written into the previously selected queue on this WCLK edge and on the next rising
WCLK also, providing that WEN is LOW). Two WCLK rising edges after write queue select, data can be
written into the newly selected queue.
The second function of the WRADD bus is to select the device of queues to be loaded on to the PAFn bus
during strobed flag mode. The most significant 3 bits, WRADD[6:3] are again used to select 1 of 8 possible
multi-queue devices that may be connected in expansion mode. Address bits WRADD[2:0] are don’t care
during device selection. The device address present on the WRADD bus will be selected on the rising
edge of WCLK provided that FSTR is HIGH, (note, that data can be written into the previously selected
queue on this WCLK edge). Please refer to Table 1 for details on the WRADD bus.
These are V
These are Ground pins and must all be connected to the GND supply rail.
CC
power supply pins and must all be connected to a +3.3V supply rail.
10
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES