IDT72V51353L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51353L7-5BB8 Datasheet - Page 7

• Manufacturer Part Number: IDT72V51353L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51353L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51353L7-5BB8

PIN DESCRIPTIONS (CONTINUED)
IDT72V51333/72V51343/72V51353 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
FSYNC
(Continued)
FXI
FXO
ID[2:0]
IW
MAST
MRS
OE
OV
OW
PAE
Symbol
(1)
(1)
(1)
(1)
PAFn Bus Sync
PAFn Bus
Expansion In
PAFn Bus
Expansion Out
Device ID Pins
Input Width
Master Device
Master Reset
Output Enable
Output Valid Flag
Output Width
Programmable
Almost-Empty Flag
Name
OUTPUT device1 on to the PAFn bus outputs, the second WCLK rising edge loads device 2 and so on. During the
OUTPUT PAFn bus operation has been selected . FXO of device ‘N’ connects directly to FXI of device ‘N+1’. This
OUTPUT data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That
OUTPUT for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected
I/O TYPE
LVTTL
LVTTL
INPUT
LVTTL
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
LVTTL
LVTTL
INPUT
LVTTL
loaded on to the PAFn bus outputs sequentially based on WCLK. The first WCLK rising edge loads
WCLK cycle that a selected device is placed on to the PAFn bus, the FSYNC output will be HIGH.
The FXI input is used when multi-queue devices are connected in expansion mode and Polled PAFn
bus operation has been selected. FXI of device ‘N’ connects directly to FXO of device ‘N-1’. The FXI
receives a token from the previous device in a chain. In single device mode the FXI input must be tied
LOW if the PAFn bus is operated in direct mode. If the PAFn bus is operated in polled mode the FXI input
must be connected to the FXO output of the same device. In expansion mode the FXI of the first device
should be tied LOW, when direct mode is selected.
FXO is an output that is used when multi-queue devices are connected in expansion mode and Polled
pin pulses HIGH when device N places its PAF status on to the PAFn bus with respect to WCLK. This pulse
(token) is then passed on to the next device in the chain ‘N+1’ and on the next WCLK rising edge the first
quadrant of device N+1 will be loaded on to the PAFn bus. This continues through the chain and FXO
of the last device is then looped back to FXI of the first device. The FSYNC output of each device in the
chain provides synchronization to the user of this looping event.
For the 8Q multi-queue device the WRADD address bus is 6 bits and RDADD address bus is 7 bits wide.
When a queue selection takes place the 3 MSb’s of this address bus are used to address the specific device
(the LSb’s are used to address the queue within that device). During write/read operations the 3 MSb’s
of the address are compared to the device ID pins. The first device in a chain of multi-queue’s (connected
in expansion mode), may be setup as ‘000’, the second as ‘001’ and so on through to device 8 which is
‘111’, however the ID does not have to match the device order. In single device mode these pins should
be setup as ‘000’ and the 3 MSb’s of the WRADD and RDADD address busses should be tied LOW. The
ID[2:0] inputs setup a respective devices ID during master reset. These ID pins must not toggle during
any device operation. Note, the device selected as the ‘Master’ does not have to have the ID of ‘000’.
IW selects the bus width for the data input bus. If IW is LOW during a Master Reset then the bus width
is x18, if HIGH then it is x9.
The state of this input at Master Reset determines whether a given device (within a chain of devices), is the
Master device or a Slave. If this pin is HIGH, the device is the master, if it is LOW then it is a Slave. The master
preventing bus contention. If a multi-queue device is being used in single device mode, this pin must
be set HIGH.
A master reset is performed by taking MRS from HIGH to LOW, to HIGH. Device programming is required
after master reset.
The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue
data output bus, Qout. If a device has been configured as a “Master” device, the Qout data outputs will
be in a Low Impedance condition if the OE input is LOW. If OE is HIGH then the Qout data outputs will be
in High Impedance. If a device is configured a “Slave” device, then the Qout data outputs will always be
in High Impedance until that device has been selected on the Read Port, at which point OE provides three-
state of that respective device.
This output flag provides output valid status for the data word present on the multi-queue flow-control device
is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the OV flag
represents the data in that respective queue. When a selected queue on the read port is read to empty,
the OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-
Impedance capability, required when multiple devices are used and the OV flags are tied together.
OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width
is x18, if HIGH then it is x9.
This pin provides the Almost-Empty flag status for the queue that has been selected on the output port
queue is almost-empty. This flag output may be duplicated on one of the PAEn bus lines. This flag is
synchronized to RCLK.
device is the first to take control of all outputs after a master reset, all slave devices go to High-Impedance,
7
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES