IDT72V51433L7-5BB8 IDT, Integrated Device Technology Inc, IDT72V51433L7-5BB8 Datasheet - Page 2

• Manufacturer Part Number: IDT72V51433L7-5BB8
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51433L7-5BB8

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51433L7-5BB8

DESCRIPTION:
vices are single chip within which anywhere between 1 and 16 discrete FIFO
queues can be setup. All queues within the device have a common data input
bus, (write port) and a common data output bus, (read port). Data written into
the write port is directed to a respective queue via an internal de-multiplex
operation, addressed by the user. Data read from the read port is accessed
from a respective queue via an internal multiplex operation, addressed by the
user. Data writes and reads can be performed at high speeds up to 166MHz,
with access times of 3.7ns. Data write and read operations are totally
independent of each other, a queue maybe selected on the write port and a
different queue on the read port or both ports may select the same queue
simultaneously.
selected for write and read operations respectively. Also a Programmable
Almost Full and Programmable Almost Empty flag for each queue is provided.
Two 8 bit programmable flag busses are available, providing status of queues
not selected for write or read operations. When 8 or less queues are configured
in the device these flag busses provide an individual flag per queue, when
more than 8 queues are used, either a Polled or Direct mode of bus operation
provides the flag busses with all queues status.
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
The IDT72V51433/72V51443/72V51453 multi-queue flow-control de-
The device provides Full flag and Output Valid flag status for the queue
2
wide. When Bus Matching is used the device ensures the logical transfer of data
throughput in a Little Endian manner.
to program the total number of queues between 1 and 16, the individual queue
depths being independent of each other. The programmable flag positions are
also user programmable. All programming is done via a dedicated serial port.
If the user does not wish to program the multi-queue device, a default option is
available that configures the device in a predetermined manner.
Reset latches in all configuration setup pins and must be performed before
programming of the device can take place. A Partial Reset will reset the read and
write pointers of an individual queue, provided that the queue is selected on both
the write port and read port at the time of partial reset.
fully functional Boundary Scan feature, compliant with IEEE 1149.1 Standard
Test Access Port and Boundary Scan Architecture.
of the functional blocks within the device.
Bus Matching is available on this device, either port can be 9 bits or 18 bits
The user has full flexibility configuring queues within the device, being able
Both Master Reset and Partial Reset pins are provided on this device. A Master
A JTAG test port is provided, here the multi-queue flow-control device has a
See Figure 1, Multi-Queue Flow-Control Device Block Diagram for an outline
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES