IDT89HPES16T4AG2ZBAL IDT, Integrated Device Technology Inc, IDT89HPES16T4AG2ZBAL Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES16T4AG2ZBAL
• Description: IC PCI SW 16LANDE 4PORT 324FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4AG2ZBAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T4AG2ZBAL

Pin Description
pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero
(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES16T4AG2 Data Sheet
The following tables list the functions of the pins provided on the PES16T4AG2. Some of the functions listed may be multiplexed onto the same
PEREFCLKP
PEREFCLKN
PE0RN[3:0]
PE1RN[3:0]
PE2RN[3:0]
PE3RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3TP[3:0]
PE3TN[3:0]
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Signal
Signal
Type
Type
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 3.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is set at 100 MHz.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus which operates at 400 KHz.
Master SMBus Data. This bidirectional signal is used for data on the mas-
ter SMBus which operates at 400 KHz.
Slave SMBus Clock. This bidirectional signal is used to synchronize trans-
fers on the slave SMBus.
Slave SMBus Data. This bidirectional signal is used for data on the slave
SMBus.
Table 1 PCI Express Interface Pins
Table 2 SMBus Interface Pins
4 of 30
Name/Description
Name/Description
September 13, 2010