IDT89HPES16T4AG2ZBAL IDT, Integrated Device Technology Inc, IDT89HPES16T4AG2ZBAL Datasheet - Page 6

• Manufacturer Part Number: IDT89HPES16T4AG2ZBAL
• Description: IC PCI SW 16LANDE 4PORT 324FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES16T4AG2ZBAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES16T4AG2ZBAL

IDT 89HPES16T4AG2 Data Sheet
SWMODE[2:0]
P01MERGEN
P23MERGEN
JTAG_TCK
JTAG_TDI
Signal
CCLKDS
CCLKUS
PERSTN
Signal
Type
Type
I
I
I
I
I
I
I
I
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each down-
stream port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by
modifying the SCLK bit in the P0_PCIELSTS register.
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally via a 90K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port
0. When this pin is high, port 0 and port 1 are not merged, and each oper-
ates as a single x4 port.
Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally via a 90K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port
2. When this pin is high, port 2 and port 3 are not merged, and each oper-
ates as a single x4 port.
Fundamental Reset. Assertion of this signal resets all logic inside
PES16T4AG2 and initiates a PCI Express fundamental reset.
Switch Mode. These configuration pins determine the PES16T4AG2
switch operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0x7 Reserved
These pins should be static and not change following the negation of
PERSTN.
JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
Table 5 Test Pins (Part 1 of 2)
Table 4 System Pins
6 of 30
Name/Description
Name/Description
September 13, 2010