IDT72T6480L10BB IDT, Integrated Device Technology Inc, IDT72T6480L10BB Datasheet - Page 25

• Manufacturer Part Number: IDT72T6480L10BB
• Description: IC FLOW-CTRL 48BIT 10NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L10BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L10BB

MEMORY CONFIGURATION (MIC[2:0])
Configurations for more information.
MEMORY SPEED (MSPEED)
for the external memory used. If MSPEED is HIGH, external memory CK and
CK will be operating at 166MHz. If MSPEED is LOW, then the external memory
CK and CK will be operating at 133MHz.
MASTER CLOCK (MCLK)
interface.
MEMORY TYPE (MTYPE[1:0])
used. See Table 14, MTYPE[1:0] Configurations for selection of the memory
density configuration.
TABLE 14 – MTYPE[1:0] CONFIGURATIONS
DEPTH EXPANSION MODE SELECT (IDEM)
mode. If this pin is tied HIGH, then the FF/IR signal will be inverted to provide
a seamless depth expansion interface. If this pin is tied LOW, the depth expansion
in IDT Standard mode will be deactivated. For details on depth expansion
configuration, see Figure 34, Depth Expansion Configuration in IDT Standard
Mode and Figure 35, Depth Expansion Configuration in FWFT Mode.
SERIAL READ ENABLE (SREN)
programmable offset registers. By setting the JSEL pin to LOW, the serial data
output (SO) and serial clock (SCLK) signals can be used with SREN to program
the offset registers. When SREN is LOW, data at the SO can be read from the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
read enable is HIGH, the reading of the offset registers will stop. SREN must be
kept LOW in order to read the entire contents of the scan out register. If at any
point SREN is toggled HIGH, the read pointer of the offset registers will reset to
the first location. The next time SREN is enabled the first contents in the offset
register will be read back. Serial read enable functions the same way in both
IDT Standard and FWFT modes. See Figure 30, Reading of Programmable
Flag Registers, for the timing diagram.
SERIAL WRITE ENABLE (SWEN)
programmable offset registers. By setting the JSEL pin to LOW, the serial input
(SI) and serial clock (SCLK) signals can be used with SWEN to program the
offset registers. When SWEN is LOW, data at the SI input are loaded into the offset
register, one bit for each LOW-to-HIGH transition of SCLK. When SWEN is
HIGH, the offset registers retain the previous settings and no offsets are loaded.
Serial write enable functions the same way in both Standard IDT and FWFT
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
MTYPE0
MTYPE1
These signals enable the EDC feature of the device. See Table 8, MIC[2:0]
This pin is used to determine the memory interface clock speed (CK and CK)
33MHz reference clock used to generate CK and CK for external memory
These signals select the density configuration of the external DDR SDRAM
This select pin is used for depth expansion configuration in IDT Standard
The serial read enable input is an enable used for reading the value of the
The serial write enable input is an enable used for serial programming of the
4M x 32
0
0
Density Configurations
8M x 32
0
1
Reserved
1
0
16M x 16
1
1
25
modes. See Figure 29, Serial Loading of Programmable Flag Registers, for
the timing diagram.
I/O VDDQ SELECT (IOSEL)
3.3V voltage signals. If IOSEL is HIGH, then all I/Os will be 2.5V levels. If IOSEL
is LOW, then all I/Os will be 3.3V levels. See Table 15, Parameters affected by
I/O selection for a list of affected I/O signals.
TABLE 15 – PARAMETERS AFFECTED
BY I/O SELECTION
NOTE
1. I/O to DDR SDRAM is not affected by I/O voltage selection
JTAG SELECT (JSEL)
This input determines whether the JTAG port will be activated or deactivated.
If JSEL is HIGH, then the JTAG port is activated and the associated JTAG pins
(TCK, TDI, TDO, TMS) are used for the boundary-scan function. If JSEL is
LOW, the JTAG port is disabled and the serial programming pins (SCLK, SI,
SO) will be used to program and read the offset register values for PAE and
PAF. See Figure 29 and 30, Serial Loading and Reading of Programmable
Registers for information on how to program the registers.
OUTPUTS
FULL FLAG/INPUT READY (FF/IR)
is selected. When the SFC is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the SFC is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW See Figure 12, Full Boundary
- IDT Standard Mode, for the relevant timing information.
memory space is available for writing in data. When there is no longer any free
space left, IR goes HIGH, inhibiting further write operations. If no reads are
performed after a reset (either MRS or PRS), IR will go HIGH see Figure 9 Write
First Word Cycles - FWFT Mode, for the relevant timing information.
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to de-assert IR is one greater than needed to
assert FF in IDT Standard mode.
double register-buffered outputs.
ASYR
ASYW
BM[3:0]
D[47:0]
EF/OR
FF/IR
FSEL[1:0]
FWFT
IDEM
IOSEL
JSEL
This input determines whether the inputs and outputs will tolerate a 2.5V or
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW when
The IR status not only measures the contents of the SFC memory, but also
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
SFC I/O affected by I/O selection
:
MIC[2:0]
MCLK
MRS
MSPEED
MTYPE[1:0]
OE
PAE
PAF
PRS
Q[47:0]
RCLK/RD
RCS
REN
SREN
SWEN
TCK/SCLK
TDI/SI
TDO/SO
TMS
WCLK/WR
WCS
WEN
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
A[12:0]
BA[1:0]
CK
CK
CAS
DDR SDRAM I/O -
FEBRUARY 10, 2009
NOT affected
DQ[63:0]
DQS[7:0]
RAS
WE
(1)