IDT72T6480L10BB IDT, Integrated Device Technology Inc, IDT72T6480L10BB Datasheet - Page 4

• Manufacturer Part Number: IDT72T6480L10BB
• Description: IC FLOW-CTRL 48BIT 10NS 324-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72T6480L10BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72T6480L10BB

DESCRIPTION
a seamless connection to external DDR SDRAM for significant storage
capacity supporting high-speed applications. Both read and write ports of the
sequential flow-control can operate independently at up to 133MHz. There
is a user selectable correction feature that will correct any erroneous single
data bit when reading from the SDRAM.
clocks, enables, and chip selects. Both ports can operate either synchro-
nously or asynchronously. Other features include bus-matching, program-
mable status flags with selectable synchronous/asynchronous timing modes,
IDT Standard or FWFT mode timing, and JTAG boundary scan functionality.
to x48, x24, or x12 bus width. There are four default offset values available
IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE
x12, x24, x48 BIT WIDE CONFIGURATION
The IDT72T6480 sequential flow-control device is a device incorporating
The independent read and write ports each has associated read and write
The bus-matching feature will allow the inputs and outputs to be configured
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for the programmable flags (PAE/PAF), as well as the option of serially
programming the offsets to a specific value.
core voltage with selectable 2.5V or 3.3V I/Os. The I/O interface to the SDRAM
will be 2.5V SSTL_2 only and not 3.3V tolerant. Both industrial and commercial
temperature ranges will be offered.
128Mb or 256Mb. The device will support industry standard DDR specification
memories (note DDR II is not supported), which include vendors such as
Samsung, Micron, and Infineon. The data bus connected to the DDR SDRAM
can be 16-bit, 32-bit, or 64-bits wide. The sequential flow-control device can
independently control up to four separate external memories for a maximum of
density of 1Gb (128MB). Depth expansion mode is available for applications
that require more than 1Gb of storage memory.
The device package is 19mm x 19mm 324-pin PBGA. It operates at a 2.5V
The sequential flow-control device controls individual DDR SDRAM of either
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 10, 2009