IDT72V51356L7-5BB IDT, Integrated Device Technology Inc, IDT72V51356L7-5BB Datasheet - Page 45

• Manufacturer Part Number: IDT72V51356L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51356L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51356L7-5BB

Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + t
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + t
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q0.
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WRADD
WADEN
WCLK
PAF
(Device 1)
PAF
(Device 2)
WEN
RCLK
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + t
De-assertion: t
If t
PAF
WCLK
REN
WEN
SKEW2
Din
t
is violated there will be one extra WCLK cycle.
CLKL
HIGH-Z
SKEW2
t
AS
t
QS
+ WCLK + t
WAF
D
t
*A*
1
ENS
Q
2
WAF
t
QH
t
AH
D - (m+1) words in Queue
t
CLKL
t
ENH
*B*
Figure 22. Almost Full Flag Timing and Queue Switch
D
1
t
1
ENS
Q
t
Figure 23. Almost Full Flag Timing
DS
2
W
*C*
D-m
t
t
t
FFHZ
2
ENH
DH
t
45
AFLZ
t
WAF
t
t
AS
QS
D
t
ENS
*D*
1
Q
1
0
t
t
SKEW2
QH
t
AH
D - m words in Queue
t
ENH
*E*
WAF
2
.
COMMERCIAL AND INDUSTRIAL
t
WAF
TEMPERATURE RANGES
*F*
WAF
1
latency.
t
WAF
t
WAF
D-(m+1) words
in Queue
5936 drw25
5936 drw26