IDT72P51339L6BBI IDT, Integrated Device Technology Inc, IDT72P51339L6BBI Datasheet - Page 14

• Manufacturer Part Number: IDT72P51339L6BBI
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51339L6BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51339L6BBI

PIN DESCRIPTIONS (CONTINUED)
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
SCLK
(N3)
SENI
(M2)
SENO
(M1)
SI
(L1)
SO
(M3)
TCK
(A8)
TDI
(B9)
TDO
(A9)
TMS
(B8)
TRST
(C7)
WADEN
(P4)
Symbol &
(Pin No.)
(2)
(2)
(2)
(2)
(2)
Serial Clock
Serial Input
Serial Output
Serial In
Serial Out
JTAG Clock
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input
JTAG Test Data HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
Output
JTAG Mode
Select
JTAG Reset
Write Address
Enable
Enable
Enable
Name
HSTL-LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input
HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device
HSTL-LVTTL During serial programming this pin is loaded with the serial data that will configure the multi-queue devices.
HSTL-LVTTL This output is used in expansion configuration and allows serial data to be passed through devices in the
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
HSTL-LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to
OUTPUT
OUTPUT
OUTPUT
I/O TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
on the rising edge of SCLK provided that SENI is enabled, LOW. When expansion of devices is performed
the SCLK of all devices should be connected to the same source.
part (via a rising edge of SCLK), provided the SENI input of that device is LOW. If multiple devices are
cascaded, the SENI input should be connected to the SENO output of the previous device. So when serial
loading of a given device is complete, its SENO output goes LOW, allowing the next device in the chain
to be programmed (SENO will follow SENI of a given device once that device is programmed). The SENI
input of the master device (or single device), should be controlled by the user.
has been completed. SENO follows SENI once programming of a device is complete. Therefore, SENO
will go LOW after programming provided SENI is LOW, once SENI is taken HIGH again, SENO will also
go HIGH. When the SENO output goes LOW, the device is ready to begin normal read/write operations.
If multiple devices are cascaded and serial programming of the devices will be used, the SENO output
should be connected to the SENI input of the next device in the chain. When serial programming of the
first device is complete, SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the SENO output
essentially follows the SENI input. The user should monitor the SENO output of the final device in the chain.
When this output goes LOW, serial loading of all devices has been completed.
Data present on SI will be loaded on a rising edge of SCLK provided that SENI is LOW. In expansion
mode the serial data input is loaded into the first device in a chain. When that device is loaded and its SENO
has gone LOW, the data present on SI will be directly output to the SO output. The SO pin of the first device
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
chain to complete programming of all devices. The SI of a device connects to SO of the previous device
in the chain. The SO of the final device in a chain should not be connected.
operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction
Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in
SHIFT-DR and SHIFT-IR controller states.
device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure
proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An
internal pull-up resistor forces TRST HIGH if left unconnected.
be written in to. A queue addressed via the WRADD bus is selected on the rising edge of WCLK provided
that WADEN is HIGH. WADEN should be asserted (HIGH) only during a queue change cycle(s). WADEN
should not be permanently tied HIGH. WADEN cannot be HIGH for the same WCLK cycle as FSTR. Note,
14
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005