IDT72P51339L6BBI IDT, Integrated Device Technology Inc, IDT72P51339L6BBI Datasheet - Page 3

• Manufacturer Part Number: IDT72P51339L6BBI
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51339L6BBI

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51339L6BBI

Figure 1. Multi-Queue Flow-Control Device Block Diagram .............................................................................................................................................. 6
Figure 2a. AC Test Load ................................................................................................................................................................................................ 19
Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19
Figure 3. Reference Signals .......................................................................................................................................................................................... 22
Figure 4. Device Programming Hierarchy ..................................................................................................................................................................... 24
Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25
Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................ 25
Figure 7. Write Port Switching Queues Signal Sequence ................................................................................................................................................ 29
Figure 8. Switching Queues Bus Efficiency ..................................................................................................................................................................... 29
Figure 9. Simultaneous Queue Switching ....................................................................................................................................................................... 30
Figure 10. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 31
Figure 11. Switching Queues Bus Efficiency ................................................................................................................................................................... 31
Figure 12. Simultaneous Queue Switching ..................................................................................................................................................................... 32
Figure 13. MARK and Re-Write Sequence .................................................................................................................................................................... 33
Figure 14. MARK and Re-Read Sequence ................................................................................................................................................................... 33
Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK ............................................................................................................................. 34
Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................ 34
Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................ 35
Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ............................................................................................................... 35
Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ............................................................................................................................... 37
Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK .............................................................................................................................. 37
Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38
Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK ................................................................................................................. 38
Figure 23. Leaving a MARK active on the Write Port ...................................................................................................................................................... 39
Figure 24. Leaving a MARK active on the Read Port ..................................................................................................................................................... 39
Figure 25. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 40
Figure 26. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 40
Figure 27. 36bit to 36bit word configuration .................................................................................................................................................................... 49
Figure 28. 36bit to 18bit word configuration .................................................................................................................................................................... 49
Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49
Figure 30. 18bit to 36bit word configuration .................................................................................................................................................................... 50
Figure 31. 18bit to 18bit word configuration .................................................................................................................................................................... 50
Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50
Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51
Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51
Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................ 51
Figure 36. Bus-Matching Byte Arrangement ................................................................................................................................................................... 53
Figure 37. Master Reset ................................................................................................................................................................................................ 54
Figure 38. Default Programming .................................................................................................................................................................................... 55
Figure 39. Parallel Programming ................................................................................................................................................................................... 56
Figure 40. Queue Programming via Write Address Bus .................................................................................................................................................. 57
Figure 41. Queue Programming via Read Address Bus ................................................................................................................................................. 57
Figure 42. Serial Port Connection for Serial Programming .............................................................................................................................................. 57
Figure 43. Serial Programming ...................................................................................................................................................................................... 58
Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................ 59
Figure 45. Write Queue Select and Mark ....................................................................................................................................................................... 60
Figure 46. Write Operations in First Word Fall Through mode ....................................................................................................................................... 61
Figure 47. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 62
Figure 48. Read Queue Select, Read Operation (IDT mode) ......................................................................................................................................... 63
Figure 49. Read Queue Select, Read Operation (FWFT mode) ..................................................................................................................................... 64
Figure 50. Read Queue Select and Mark (IDT mode) .................................................................................................................................................... 65
Figure 51. Output Ready Flag Timing (In FWFT Mode) ................................................................................................................................................. 66
Figure 52. Read Queue Selection with Read Operations (IDT mode) ............................................................................................................................. 67
Figure 53. Read Queue Select, Read Operation and OE Timing .................................................................................................................................... 68
Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................ 69
IDT72P51339/72P51349/72P51359/72P51369 1.8V, MQ FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
List of Figures
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AUGUST 4, 2005