IDT72P51539L6BB IDT, Integrated Device Technology Inc, IDT72P51539L6BB Datasheet - Page 13

• Manufacturer Part Number: IDT72P51539L6BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51539L6BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51539L6BB

PIN DESCRIPTIONS (CONTINUED)
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
PR
(R9)
Q[35:0]
Qout
(See Pin No.
table for details)
QSEL[1:0]
(QSEL1-K1
QSEL0-J2
RADEN
(R14)
RCLK
(T10)
RCS
(R10)
RDADD
[7:0]
(RDADD7-P16
RDADD6-P15
RDADD5-P14
RDADD4-N16
RDADD3-N15
RDADD2-N14
RDADD1-M16
RDADD0-M15)
REN
(T11)
Symbol &
Pin No.
Packet Ready
Data Output Bus HSTL-LVTTL These are the 36 data output pins. Data is read out of the device via these output pins on the rising edge
Queue Select
Read Address
Read Clock
Read Chip
Select
Read Address
Bus
Read Enable
Enable
Flag
Name
HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected
HSTL-LVTTL The QSEL pins provides various queue programming options. Refer to Table 2, for details.
HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to
HSTL-LVTTL When enabled by REN, the rising edge of RCLK reads data from the selected queue via the output
HSTL-LVTTL The RCS signal in concert with REN signal provides control to enable data on to the output read data bus.
HSTL-LVTTL For the 32Q device the RDADD bus is 8 bits. The RDADD bus is a dual purpose address bus. The first
HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK.
I/O TYPE
OUTPUT
OUTPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
for read operations. During a master reset the state of the PKT input determines whether Packet mode
of operation will be used. If Packet mode is selected, then the condition of the PR flag and EF/OR signal
are asserted indicates a packet is ready for reading. The user must mark the start of a packet and the end
of a packet when writing data into a queue. Using the Start Of Packet (SOP) and End Of Packet (EOP)
markers, the multi-queue device sets PR LOW if one or more “complete” packets are available in the queue.
A complete packet(s) must be written before the user is allowed to switch queues.
of RCLK provided that REN is LOW, OE is LOW and the Queue is selected. Note, that in Packet Ready
mode Q32-Q35 may be used as packet markers, please see packet ready functional discussion for more
detail. Due to bus matching not all outputs may be used, any unused outputs should not be connected.
1. A QSEL value of 00, enables the user to program the number of queues using the Write Address bus.
2. A QSEL value of 01, enables the user to program the number of queues using the Read Address bus.
3. A QSEL value of 10, Selects a configuration of 16 queues.
4. A QSEL value of 11, selects a configuration of 32 queues
be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided
that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN
should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,
that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the
part has been completed and SENO has gone LOW.
bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK
while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the
PAEn/PRn flag status word to be placed on the PAEn/PRn bus during direct flag operation. During polled
flag operation the PAEn/PRn bus is cycled with respect to RCLK and the ESYNC signal is synchronized
to RCLK. The PAE, PR and OR outputs are all synchronized to RCLK. During device expansion the EXO
and EXI signals are based on RCLK. RCLK must be continuous and free-running.
During a Master Reset cycle the RCS it is don’t care signal.
function of RDADD is to select a Queue to be read from. The least significant 5 bits of the bus, RDADD[4:0]
are used to address 1 of 32 possible queues within a multi-queue device. The most significant 3 bits,
RDADD[7:5] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion
mode. An in expansion configuration the 3 MSb’s will address a device with the matching ID code. The
address present on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is
HIGH, (note, that data can be placed on to the Qout bus, read from the previously selected queue on this
RCLK edge). Two RCLK rising edges after read queue select, data will be placed on to the Qout outputs
from the newly selected queue, regardless of REN due to the first word fall through effect.
The second function of the RDADD bus is to select the status word of queues to be loaded on to the
PAEn/PRn bus during strobed flag mode. The least significant 4 bits, RDADD[3:0] are used to select the
status word of a device to be placed on the PAEn bus. The most significant 3 bits, RDADD[7:5] are again
used to select 1 of 8 possible multi-queue devices that may be connected in expansion configuration.
Address bits RDADD[4] is don’t care during status word selection. The status word address present
on the RDADD bus will be selected on the rising edge of RCLK provided that ESTR is HIGH, (note, that
data can be placed on to the Qout bus, read from the previously selected Queue on this RCLK edge).
Please refer to Table 5 for details on RDADD bus.
In the FWFT mode, a queue to be read from can be selected via RCLK, RADEN and the RDADD address
bus regardless of the state of REN. A read enable is not required to cycle the PAEn/PRn bus (in polled
mode) or to select the PAEn status word, (in direct mode).
13
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009