IDT72P51539L6BB IDT, Integrated Device Technology Inc, IDT72P51539L6BB Datasheet - Page 15

• Manufacturer Part Number: IDT72P51539L6BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51539L6BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51539L6BB

PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. Inputs should not change after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 82-86 and Figures 71-73.
(See pg. 16)
IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592
WADEN
(Continued)
WCLK
(T7)
WCS
(T8)
WEN
(T6)
WRADD
[7:0]
(WRADD7-T1
WRADD6-R1
WRADD5-R2
WRADD4-P1
WRADD3-P2
WRADD2-P3
WRADD1-N1
WRADD0-N2)
V
V
(See pg. 16)
GND
(See pg. 16)
Vref
(K3)
DD
DDQ
Symbol &
Pin No.
Write Address
Enable
Write Clock
Write Chip
Select
Write Enable
Write Address
Bus
+1.8V Supply
O/P Rail Voltage
Ground Pin
Reference
Voltage
Name
HSTL-LVTTL that a write queue selection cannot be made, (WADEN must NOT go active) until programming of the part
HSTL-LVTTL When enabled by WEN, the rising edge of WCLK writes data into the selected Queue via the input
HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
HSTL-LVTTL The WEN input enables write operations to a selected Queue based on a rising edge of WCLK. A
HSTL-LVTTL For the 32Q device the WRADD bus is 8 bits. The WRADD bus is a dual purpose address bus. The
I/O TYPE
Ground
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Power
Power
HSTL
has been completed and SENO has gone LOW.
bus, Din. The Queue to be written to is selected via the WRADD address bus and a rising edge of
WCLK while WADEN is HIGH. A rising edge of WCLK in conjunction with FSTR and WRADD will also
select the flag status word to be placed on the PAFn bus during direct flag operation. During polled flag
operation the PAFn bus is cycled with respect to WCLK and the FSYNC signal is synchronized to WCLK.
The PAFn, PAF and FF outputs are all synchronized to WCLK. During device expansion the FXO and
FXI signals are based on WCLK. The WCLK must be continuous and free-running.
queue to be written to can be selected via WCLK, WADEN and the WRADD address bus regardless
of the state of WEN. Data present on Din can be written to a newly selected queue on the second WCLK
cycle after queue selection provided that WEN is LOW. A write enable is not required to cycle the PAFn
bus (in polled mode) or to select the PAFn status word , (in direct mode).
first function of WRADD is to select a Queue to be written to. The least significant 5 bits of the bus,
configuration the most significant 3 bits, WRADD[7:5] are used to select 1 of 8 possible multi-queue devices
(dependant on the number of queues addressed) that may be connected in expansion configuration. These
3 MSb’s will address a device with the matching ID code. The address present on the WRADD bus will
be selected on a rising edge of WCLK provided that WADEN is HIGH, (note, that data present on the Din
bus can be written into the previously selected queue on this WCLK edge and on the next rising WCLK
also, providing that WEN is LOW). Two WCLK rising edges after write queue select, data can be written
The second function of the WRADD bus is to select the status word of queues to be loaded on to the PAFn
bus during strobed flag mode. The least significant 4 bits, WRADD[3:0] are used to select the status word
of a device to be placed on the PAFn bus. The most significant 3 bits, WRADD[7:5] are again used to
select 1 of 8 possible multi-queue devices that may be connected in expansion configuration. Address bits
WRADD[4] is don’t care during status word selection. The status word address present on the WRADD
bus will be selected on the rising edge of WCLK provided that FSTR is HIGH, (note, that data can be
written into the previously selected queue on this WCLK edge). Please refer to Table 4 for details on the
WRADD bus.
These are V
to +2.5V, for HSTL these pins must be connected to +1.5V and for eHSTL these pins must be connected
to +1.8V.
These are Ground pins and must all be connected to the GND supply rail.
This is a Voltage Reference input and must be connected to a voltage level determined from the table
"Recommended DC Operating Conditions". The input provides the reference level for HSTL/eHSTL
inputs. For LVTTL I/O mode this input should be tied to GND.
WRADD[4:0] are used to address 1 of 32 possible queues within a multi-queue device. In expansion
into the newly selected queue.
These pins must be tied to the desired output rail voltage. For LVTTL I/O these pins must be connected
DD
power supply pins and must all be connected to a +1.8V supply rail.
15
Description
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FEBRUARY 13, 2009