IDT89HPES24T6G2ZBAL IDT, Integrated Device Technology Inc, IDT89HPES24T6G2ZBAL Datasheet - Page 4

• Manufacturer Part Number: IDT89HPES24T6G2ZBAL
• Description: IC PCI SW 24LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24T6G2ZBAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES24T6G2ZBAL

Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
IDT 89HPES24T6G2 Data Sheet
The following tables list the functions of the pins provided on the PES24T6G2. Some of the functions listed may be multiplexed onto the same pin.
1.
REFCLKM is not available in the 19mm package and frequency is set at 100MHz.
MSMBADDR[4:1]
PEREFCLKP
PEREFCLKN
PE0RN[3:0]
PE1RN[3:0]
PE2RN[3:0]
PE3RN[3:0]
PE4RN[3:0]
PE5RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE1RP[3:0]
PE1TP[3:0]
PE1TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE3RP[3:0]
PE3TP[3:0]
PE3TN[3:0]
PE4RP[3:0]
PE4TP[3:0]
PE4TN[3:0]
PE5RP[3:0]
PE5TP[3:0]
PE5TN[3:0]
REFCLKM
MSMBCLK
Signal
Signal
1
1
Type
I/O
Type
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Table 3 SMBus Interface Pins (Part 1 of 2)
Master SMBus Address. These pins determine the SMBus address of the
serial EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize
transfers on the master SMBus.
Table 2 PCI Express Interface Pins
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit
pairs for port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive
pairs for port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit
pairs for port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pairs for port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit
pairs for port 2.
PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pairs for port 3.
PCI Express Port 3 Serial Data Transmit. Differential PCI Express transmit
pairs for port 3.
PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pairs for port 4.
PCI Express Port 4 Serial Data Transmit. Differential PCI Express transmit
pairs for port 4.
PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pairs for port 5.
PCI Express Port 5 Serial Data Transmit. Differential PCI Express transmit
pairs for port 5.
PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
This pin should be static and not change following the negation of
PERSTN.
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Name/Description
Name/Description
February 11, 2009