IDT89HPES24T6G2ZBAL IDT, Integrated Device Technology Inc, IDT89HPES24T6G2ZBAL Datasheet - Page 6

• Manufacturer Part Number: IDT89HPES24T6G2ZBAL
• Description: IC PCI SW 24LANE 6PORT 324-FCBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES24T6G2ZBAL

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES24T6G2ZBAL

IDT 89HPES24T6G2 Data Sheet
1.
MSMBSMODE
GPIO pins 3, 4, 5, 6 are not available in the 19mm package.
P01MERGEN
P23MERGEN
P45MERGEN
GPIO[10]
Signal
Signal
CCLKDS
CCLKUS
PERSTN
GPIO[8]
GPIO[9]
1
Type
Type
I/O
I/O
I/O
I
I
I
I
I
I
I
Table 4 General Purpose I/O Pins (Part 2 of 2)
General Purpose I/O.
General Purpose I/O.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P1RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 1
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P3RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 3
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: P5RSTN
Alternate function pin type: Output
Alternate function: Reset output for downstream port 5
Common Clock Downstream. The assertion of this pin indicates that all
downstream ports are using the same clock source as that provided to
downstream devices.This bit is used as the initial value of the Slot Clock
Configuration bit in all of the Link Status Registers for downstream ports.
The value may be overridden by modifying the SCLK bit in each downstream
port’s PCIELSTS register.
Common Clock Upstream. The assertion of this pin indicates that the
upstream port is using the same clock source as the upstream device. This
bit is used as the initial value of the Slot Clock Configuration bit in the Link
Status Register for the upstream port. The value may be overridden by mod-
ifying the SCLK bit in the P0_PCIELSTS register.
Master SMBus Slow Mode. The assertion of this pin indicates that the mas-
ter SMBus should operate at 100 KHz instead of 400 KHz. This value may
not be overridden.
Port 0 and 1 Merge. P01MERGEN is an active low signal. It is pulled low
internally via a 90K ohm resistor.
When this pin is low, port 0 is merged with port 1 to form a single x8 port.
The Serdes lanes associated with port 1 become lanes 4 through 7 of port 0.
When this pin is high, port 0 and port 1 are not merged, and each operates
as a single x4 port.
Port 2 and 3 Merge. P23MERGEN is an active low signal. It is pulled low
internally via a 90K ohm resistor.
When this pin is low, port 2 is merged with port 3 to form a single x8 port.
The Serdes lanes associated with port 3 become lanes 4 through 7 of port 2.
When this pin is high, port 2 and port 3 are not merged, and each operates
as a single x4 port.
Port 4 and 5 Merge. P45MERGEN is an active low signal. It is pulled low
internally via a 90K ohm resistor.
When this pin is low, port 4 is merged with port 5 to form a single x8 port.
The Serdes lanes associated with port 5 become lanes 4 through 7 of port 4.
When this pin is high, port 4 and port 5 are not merged, and each operates
as a single x4 port.
Fundamental Reset. Assertion of this signal resets all logic inside
PES24T6G2 and initiates a PCI Express fundamental reset.
Table 5 System Pins (Part 1 of 2)
6 of 50
Name/Description
Name/Description
February 11, 2009