IDT80KSBR201BR IDT, Integrated Device Technology Inc, IDT80KSBR201BR Datasheet - Page 2

• Manufacturer Part Number: IDT80KSBR201BR
• Description: IC FLOW CTRL SRL BUFFER 484CBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT80KSBR201BR

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 80KSBR201BR

„2007 Integrated Device Technology, Inc. All rights reserved.
IDT
Notes
1.0 Functional Description
on-chip memory with expansion of one QDRII SRAM externally bringing the total buffering capacity to 90Mbits of storage.
This device is built to work with any sRIO device and especially with the IDT Pre-Processing Switch (PPS) number
IDT70K2000.
traffic that is on any given port or, as a delay buffer to store data and present it at a later time. This is important in DPS
applications where time samples are compared with the previous sample such as Cellular Base Stations. Please refer to
the application note “Serial Buffer and Pre-Processing Switch”.
nates data transfers, either to or from that device. A slave is one that responds to commands from other devices to move
data. As a master, the SerB can receive data and at a pre-programmed water level (either number of packets or bytes) the
device will form and transmit either packets or status (e.g., doorbells) to a programmed location. As a slave, the device will
produce the data requested by other devices.
two memories are seamlessly connected by the Serial Buffer to form a large, 90 Mbit buffer memory. The QDR SRAM
interface runs at speeds of only 155MHz allowing lower cost memories to be used as well as easier board layout. Data
rates still support up to 10Gbits/s (OC-192) throughput in the device to maintain full sRIO four-lane compliance.
and a Programmable Almost Full and Almost Empty flag for the queue is also provided.
attached. The device treats the full amount of memory, internal or a combination of internal and external, as a single
memory block. Status flags from that queue, either referring to the writes (full flags) or the reads (empty flags) to or from
that queue represent the total amount of memory. Flags can be read from the serial port or from the I
Proactive flags can be configured to send a doorbell and/or change the interrupt pin once a flag is set. Partial full and
empty flags can be programmed to provide reaction time for writes and reads respectively. Flags associated with reaching
water marks are available in addition to the full and empty flags.
Scan feature, compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. The SerB can also
be programmed via the JTAG port. There is also an I
configuration registers.
parallel interfaces at an equivalent total bandwidth. The high-speed serial interfaces allow reduced pin count over parallel
interfaces.
2.0 Applications
2.1 Pre-Processing Switch Data Storage
storage device, holding large amounts of data passed to it by the PPS. In this application, the S-Port 1 on the SerB will
connect to one of the 4x ports of the PPS. The PPS will pass approximately 10ms of data to the SerB at which time the
SerB will start to pass it back to the PPS as a multicast. It is expected that the data flow will remain constant with 10ms (or
other designated quantity) worth of data always in storage.
The
In this configuration where multiple DSPs are used with the PPS, the SerB can function as an over-flow port to handle
The
This device can operate as a master or a slave. In the sRIO environment, a master is defined as a device that origi-
For applications requiring larger buffers, an additional 72Mbits of QDR SRAM can be attached via the Parallel Port. The
The device provides Full flag and Empty flag status for the queue selected for write and read operations respectively,
The device is configured into a single queue comprising the full internal memory and potentially the external memory if
The SerB is capable of translating between the selected protocols when more than one port is active.
A JTAG test port is provided running at 3.3V, here the multi-queue flow-control device has a fully functional Boundary
In all applications, the SerB is a low pin count device, compared with equivalent FIFO storage devices that utilize
The SerB’s primary application is for a Basestation using the IDT’s Pre-Processing Switch (PPS). The SerB will be a
The Basestation uses the data for sample scattering (noise reduction) and alignment of control and data packets.
80KSBR201
IDT80KSBR201
fully complies to sRIO specification version 1.3 and is implemented to a class 1+ end-point device.
is a Serial RapidIO
2 of 7
TM
sequential buffer (SerB) flow-control device consisting of up to 18Mbits of
2
C processor port for programming and retrieving information from the
November 26, 2007
Product Brief
2
C or JTAG port.