IDT89HPES64H16ZABR IDT, Integrated Device Technology Inc, IDT89HPES64H16ZABR Datasheet - Page 10

• Manufacturer Part Number: IDT89HPES64H16ZABR
• Description: IC PCI SW 64LANE 16PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES64H16ZABR

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES64H16ZABR

IDT 89HPES64H16 Data Sheet
P1213MERGEN
P1415MERGEN
JTAG_TRST_N
SWMODE[3:0]
JTAG_TCK
JTAG_TDO
JTAG_TMS
JTAG_TDI
RSTHALT
Signal
PERSTN
Signal
Type
Type
O
I
I
I
I
I
I
I
I
I
Port 12 and 13 Merge. P1213MERGEN is an active low signal. It is pulled low inter-
nally via a 251K ohm resistor.
When this pin is low, port 12 is merged with port13 to form a single x8 port. The
Serdes lanes associated with port 13 become lanes 4 through 7 of port 12. When this
pin is high, port 12 and port 13 are not merged, and each operates as a single x4 port.
Port 14 and 15 Merge. P1415MERGEN is an active low signal. It is pulled low inter-
nally via a 251K ohm resistor.
When this pin is low, port 14 is merged with port 15 to form a single x8 port. The
Serdes lanes associated with port 15 become lanes 4 through 7 of port 14. When this
pin is high, port 14 and port 15 are not merged, and each operates as a single x4 port.
Fundamental Reset. Assertion of this signal resets all logic inside the PES64H16 and
initiates a PCI Express fundamental reset.
Reset Halt. When this signal is asserted during a PCI Express fundamental reset, the
PES64H16 executes the reset procedure and remains in a reset state with the Master
and Slave SMBuses active. This allows software to read and write registers internal to
the device before normal device operation begins. The device exits the reset state
when the RSTHALT bit is cleared in the PA_SWCTL register by an SMBus master.
Switch Mode. These configuration pins determine the PES64H16 switch operating
mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 through 0x7 - Reserved
0x8 - Normal switch mode with upstream port failover (port 0 selected as the
0x9 - Normal switch mode with upstream port failover (port 2 selected as the
0xA - Normal switch mode with Serial EEPROM initialization and upstream port
0xB - Normal switch mode with Serial EEPROM initialization and upstream port
0xC through 0xF - Reserved
JTAG Clock. This is an input test clock used to clock the shifting of data into or out of
the boundary scan logic or JTAG Controller. JTAG_TCK is independent of the system
clock with a nominal 50% duty cycle.
JTAG Data Input. This is the serial data input to the boundary scan logic or JTAG
Controller.
JTAG Data Output. This is the serial data shifted out from the boundary scan logic or
JTAG Controller. When no data is being shifted out, this signal is tri-stated.
JTAG Mode. The value on this signal controls the test mode select of the boundary
scan logic or JTAG Controller.
JTAG Reset. This active low signal asynchronously resets the boundary scan logic
and JTAG TAP Controller. An external pull-up on the board is recommended to meet
the JTAG specification in cases where the tester can access this signal. However, for
systems running in functional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 5 System Pins (Part 2 of 2)
upstream port)
upstream port)
failover (port 0 selected as the upstream port)
failover (port 2 selected as the upstream port)
Table 6 Test Pins
10 of 49
Name/Description
Name/Description
October 7, 2008