IDT89HPES64H16ZABR IDT, Integrated Device Technology Inc, IDT89HPES64H16ZABR Datasheet - Page 5

• Manufacturer Part Number: IDT89HPES64H16ZABR
• Description: IC PCI SW 64LANE 16PORT 1156BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT89HPES64H16ZABR

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 89HPES64H16ZABR

IDT 89HPES64H16 Data Sheet
PEREFCLKN[3:0]
PEREFCLKP[3:0]
PE10RP[3:0]
PE10RN[3:0]
PE10TN[3:0]
PE11RP[3:0]
PE11RN[3:0]
PE11TN[3:0]
PE12RP[3:0]
PE12RN[3:0]
PE12TN[3:0]
PE13RP[3:0]
PE13RN[3:0]
PE13TN[3:0]
PE14RP[3:0]
PE14RN[3:0]
PE14TN[3:0]
PE15RP[3:0]
PE15RN[3:0]
PE15TN[3:0]
PE10TP[3:0]
PE11TP[3:0]
PE12TP[3:0]
PE13TP[3:0]
PE14TP[3:0]
PE15TP[3:0]
PE8RN[3:0]
PE9RN[3:0]
PE8RP[3:0]
PE8TP[3:0]
PE8TN[3:0]
PE9RP[3:0]
PE9TP[3:0]
PE9TN[3:0]
REFCLKM
Signal
Type
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 2 of 2)
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for
port 8.
PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for
port 8.
PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs
for lanes 4 through 7.
PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs
for lanes 4 through 7.
PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for
port 10.
PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs
for port 10.
PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for
port 11. When port 10 is merged with port 11, these signals become port 10 receive
pairs for lanes 4 through 7.
PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs
for port 11. When port 10 is merged with port 11, these signals become port 10 trans-
mit pairs for lanes 4 through 7.
PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pairs for
port 12.
PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pairs
for port 12.
PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pairs for
port 13. When port 12 is merged with port 13, these signals become port 12 receive
pairs for lanes 4 through 7.
PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pairs
for port 13. When port 12 is merged with port 13, these signals become port 12 trans-
mit pairs for lanes 4 through 7.
PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pairs for
port 14.
PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pairs
for port 14.
PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pairs for
port 15. When port 14 is merged with port 15, these signals become port 14 receive
pairs for lanes 4 through 7.
PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pairs
for port 15. When port 14 is merged with port 15, these signals become port 14 trans-
mit pairs for lanes 4 through 7.
PCI Express Reference Clock Mode Select. This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PCI Express Reference Clock. Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
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Name/Description
October 7, 2008