ADP3154JRU-REEL Analog Devices Inc, ADP3154JRU-REEL Datasheet - Page 10

• Manufacturer Part Number: ADP3154JRU-REEL
• Description: IC PS DUAL PENTIUM III 20-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADP3154JRU-REEL

• Rohs Status: RoHS non-compliant
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP

ADP3154
of a resistor and capacitor. The required resistor value can be
calculated from the equation:
where
and where the quantities 16.4 k and 275 k are characteristics
of the ADP3154 and the value of the current sense resistor, R
has already been determined as above.
Although a single termination resistor equal to R
the proper voltage positioning gain, the dc biasing of that resis-
tor would determine how the regulation band is centered (i.e.,
offset). Note that sometimes the specified regulation band is
asymmetrical with respect to the nominal VID voltage. With the
ADP3154, the offset is already considered part of the design
procedure—no special provision is required. To accomplish the
dc biasing, it is simplest to use two resistors to terminate the g
amplifier output, with the lower resistor tied to ground and the
upper resistor to the 12 V supply of the IC. The values of these
resistors can be calculated using:
and
where V
ommended 12 V), and V
amplifier to produce the desired offset at the output. V
calculated using Equation 2 below, where V
from the nominal VID-programmed value to the center of the
specified regulation window for the output voltage. (Note this
may be either positive or negative.) For clarification, that offset
is given by:
where V
allowed for regulation.
Finally, the compensating capacitance is determined from the
equality of the pole frequency of the error amplifier gain and the
zero frequency of the impedance of the output capacitor:
Trade-Offs Between DC Load Regulation and AC Load
Regulation
Casual observation of the circuit operation—e.g., with a voltmeter
—would make it appear that the dc load regulation appears
to be rather poor compared to a conventional regulator. This
DIV
HI
and V
is the resistor divider supply voltage (e.g., the rec-
V
Rt
OS
TOTAL
LO
V
R
OUT OS
are the respective upper and lower limits
LOWER
R
C
Rt
(
R
C
TOTAL
R
UPPER
COMP
OS
)
C
16 4 .
275
275
is the offset voltage required on the
2
1
R
(
V
C
k
k
k
C
R
HI
V
Rt
0 8
O
C
HI
.
–
V
TOTAL
V
DIV
Rt
Rt
R
V
–
V
ESR
V
LO
CS
DIV
V
TOTAL
V
OS
TOTAL
OS
LO
)–
–
V
V
VID
OUT OS
I
OS
OUT(OS)
OMAX
(
C
)
would yield
1 36
is the offset
Rt
.
TOTAL
OS
k
is
CS
m
– .
,
1 7
–10–
V
would be especially noticeable under very light or very heavy
loads where the voltage is “positioned” near one of the extremes
of the regulation window rather than near the nominal center
value. It must be noted and understood that this low gain char-
acteristic (i.e., loose dc load regulation) is inherently required to
allow improved transient containment (i.e., to achieve tighter ac
load regulation). That is, the dc load regulation is intentionally
sacrificed (but kept within specification) in order to minimize
the number of capacitors required to contain the load transients
produced by the CPU.
Linear Regulator
The ADP3154 linear regulator provides a low cost, convenient
and versatile solution for generating additional lower supply rails
that can be programmed in the range 1.2 V–5 V. The maximum
output load current is determined by the size and thermal
impedance of the external N-channel power MOSFET that is
placed in series with the supply and controlled by the ADP3154.
The output voltage, V
pin of the ADP3154 and compared to an internal 1.2 V refer-
ence in a negative feedback loop which keeps the output voltage
in regulation. If the load is being reduced or increased, the FET
drive will also be reduced or increased by the ADP3154 to pro-
vide a well regulated 1% accurate output voltage. The output
voltage is programmed by adjusting the value of the external
resistor R
Efficiency of the Linear Regulator
The efficiency and corresponding power dissipation of the linear
regulator are not determined by the ADP3154. Rather, these
are a function of input and output voltage and load current.
Efficiency is approximated by the formula:
The corresponding power dissipation in the MOSFET, together
with any resistance added in series from input to output is given
by:
Minimum power dissipation and maximum efficiency are ac-
complished by choosing the lowest available input voltage that
exceeds the desired output voltage. However, if the chosen
input source is itself generated by a linear regulator, its power
dissipation will be increased in proportion to the additional
current it must now provide. For most PC systems, the lowest
available input source for the linear regulators which is not itself
generated by a linear regulator is 3.3 V from the main power
supply.
Figure 14. Linear Regulator with Overcurrent Protection
Rt
275
V
TOTAL
I
O2
O2
k
= 0.5A
= 3.3V
PROG
P
LDO
, shown in Figure 14.
6
R I
= (V
1.1
1000 F/10V
R
CS OMAX
S2
= 100%
IN(LDO)
OLDO1
V
IN
IRLR2703
= +5V
in Figure 14, is sensed at the FB
– V
(V
OUT(LDO)
OUT
2N2222
470pF
)
R
V
35k
PROG
2k
IN
I
)
OUT(LDO)
VLDO
ADP3154
FB
20k
REV. A
(2)