ADP3154JRU-REEL Analog Devices Inc, ADP3154JRU-REEL Datasheet - Page 11

• Manufacturer Part Number: ADP3154JRU-REEL
• Description: IC PS DUAL PENTIUM III 20-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of ADP3154JRU-REEL

• Rohs Status: RoHS non-compliant
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP

Assuming that the 3.3 V supply is used to provide input power
for a 1.5 V linear regulator output, the efficiency will inherently
be 1.5 V
demand in all of the low voltage power rails (e.g., 1.5 V, 1.8 V
and 2.5 V) can produce unacceptable dissipation and junction
temperatures in the linear regulators. For such systems, Analog
Devices recommends the ADP3156—a switching regulator that
generates one of the lower voltage outputs (e.g. 1.8 V), which can
also be used as a power source to the lower voltage outputs
(e.g., 1.5 V). This results is a highly efficient and reliable power
conversion system that can readily handle the combined loading
specifications for the lower system voltages, with room to spare
for the higher current demands and lower voltages of next gen-
eration PC systems.
Features
• Tight DC Regulation due to 1% Reference and High Gain
• Output Voltage Stays Within Specified Limits at Load
• Fast Response to Input Voltage or Load Current Transients
Overcurrent protection may be provided by the addition of an
external NPN transistor and an external resistor R
specification and procedure are given below.
Linear Regulator Design Example
Maximum Ambient Temperature . . . . . . . . . . . . . T
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . V
Maximum Output Current . . . . . . . . . . . . . . . I
Maximum Output Load Transient Allowed . . . V
Chosen MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . IRLR2703
Junction-to-Ambient Thermal Impedance (MOSFET)
1
The output voltage may be programmed by the R
as follows:
The current sense resistor may be calculated as follows:
The power rating is:
Use a 0.5 W resistor.
The maximum FET junction temperature at shorted output is:
which is within the maximum allowed by the FET’s data sheet.
The maximum FET junction temperature at nominal output is:
The output filter capacitor maximum allowed ESR is:
This requirement is met using a 1000 F/10 V LXV series ca-
pacitor from United Chemicon. For applications requiring
higher output current, a heat sink and/or a larger MOSFET
REV. A
Uses 1-inch square PCB cu-foil as heat sink.
Current Step with 30 A/ s Slope
JA
T
50 C + (40 C/W
T
50 C + (40 C/W
FETMAX
FETMAX
R
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 C/W
PROG
ESR ~ V
3.3 V, which is less than 50%. The total current
= T
= T
P
1 2
S2
A
V
.
A
+ (
= R
O2
TR2
R
+ (
V
S
2
/I
–
S2
JA
OMAX
1
JA
5 V
(5 V – 3.3 V )
I
0 54
O MAX
.
(I
V
2
20
(V
= 0.036 V/0.5 A = 0.072
O2MAX
IN
V
k
IN
0.5 A
I
– V
O2MAX
0 54
0 5
.
.
1.1)
O2
3 3
1 2
.
.
A
V
)
1.1) = 160 C
V
V
2
0.5 A) = 84 C
1.1) =
= 0.33 W
1 1
I
O2MAX
.
20
k
) =
O2MAX
PROG
TR2
S2
. The design
35
O2
= 0.036 V
A
1
resistor
k
IN
= 3.3 V
= 0.5 A
= 50 C
= 5 V
–11–
should be used to reduce the MOSFET’s junction-to-ambient
thermal impedance.
LAYOUT AND COMPONENT PLACEMENT GUIDELINES
The following guidelines are recommended for optimal perfor-
mance of a switching regulator in a PC system:
General Recommendations
1.
2.
3.
4.
5.
6.
7.
For best results, a four-layer (minimum) PCB is recom-
mended. This should allow the needed versatility for con-
trol circuitry interconnections with optimal placement, a
signal ground plane, power planes for both power ground
and the input power (e.g., 5 V), and wide interconnection
traces in the rest of the power delivery current paths. Each
square unit of 1 ounce copper trace has a resistance of
Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance intro-
duced by these current paths is minimized and the via cur-
rent rating is not exceeded.
The power and ground planes should overlap each other as
little as possible. It is generally easiest (although not neces-
sary) to have the power and signal ground planes on the
same PCB layer. The planes should be connected nearest
to the first input capacitor where the input ground current
flows from the converter back to the power source (e.g.,
5 V).
If critical signal lines (including the voltage and current
sense lines of the ADP3154) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
The PGND pin of the ADP3154 should connect first to a
ceramic bypass capacitor (on the V
power ground plane using the shortest possible trace. How-
ever, the power ground plane should not extend under
other signal components, including the ADP3154 itself. If
necessary, follow the preceding guideline to use the signal
plane as a shield between the power ground plane and the
signal circuitry.
The AGND pin of the ADP3154 should connect first to the
timing capacitor (on the C
ground plane. In cases where no signal ground plane can be
used, short interconnections to other signal ground cir-
cuitry in the power converter should be used—the compen-
sation capacitor being the next most critical.
The output capacitors of the power converter should be
connected to the signal ground plan even though power
current flows in the ground of these capacitors. For this
reason, it is advised to avoid critical ground connections (e.g.,
the signal circuitry of the power converter) in the signal
ground plane between the input and output capacitors. It
is also advised to keep the planar interconnection path short
(i.e., have input and output capacitors close together).
~0.53 mW at room temperature.
T
pin), and then into the signal
CC
pin) and then into the
ADP3154