HW-USB-II-G Xilinx Inc, HW-USB-II-G Datasheet - Page 21

PLATFORM CABLE USB II

HW-USB-II-G

Manufacturer Part Number
HW-USB-II-G
Description
PLATFORM CABLE USB II
Manufacturer
Xilinx Inc
Datasheet

Specifications of HW-USB-II-G

Accessory Type
USB Platform Cable
For Use With/related Products
Xilinx FPGA, CPLDS, Platform Flash PROMs, XC18V00 PROMs, System ACE MPM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1572

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X-Ref Target - Figure 21
Input Receive Structure
Each input signal is routed through a NC7WZ07 ultra high-speed CMOS, open-drain receive buffer. Series-termination
resistors (499Ω) provide current limit protection for positive and negative excursions. Schottky diodes provide the input
buffers with undershoot protection. The receive buffers are biased by an internal 1.8V power supply. See
for V
compensating for target system drivers in multi-device chains where the last device in the chain might be referenced to a
voltage other than V
X-Ref Target - Figure 22
DS593 (v1.2.1) March 17, 2011
IL
and V
IH
specifications. The receive buffers can tolerate voltages higher than the bias voltage without damage,
REF
(for example, the TDO output at the end of a JTAG chain).
FPGA
Input
Figure 22: Target Interface Receiver Topology
Figure 21: Output Drive Voltage vs. V
V
NC7WZ07
www.xilinx.com
REF
To output buffer
Voltage (VDC)
BAT54
499Ω
REF
2 mm Connector
I/O Pin
DS593_22_021408
Platform Cable USB II
DS593_21_021408
Table 9, page 32
21

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