EVAL-AD7643CBZ Analog Devices Inc, EVAL-AD7643CBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7643CBZ
• Description: BOARD EVALUATION FOR AD7643
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7643CBZ

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 1.25M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 65mW @ 1.25MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7643
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7643
16-Bit and 8-Bit Interface (Master or Slave)
In the 16-bit (MODE[1:0] = 1) and 8-bit (MODE[1:0] = 2)
interfaces, the A0/A1 pins allow a glueless interface to a 16- or
8-bit bus, as shown in Figure 35. By connecting A0/A1 to an
address line(s), the data can be read in two words for a 16-bit
interface, or three bytes for an 8-bit interface. This interface can
be used in both master and slave parallel reading modes. Refer
to Table 7 for the full details of the interface.
SERIAL INTERFACE
The AD7643 is configured to use the serial interface when
MODE[1:0] = 3. The AD7643 outputs 18 bits of data, MSB first,
on the SDOUT pin. This data is synchronized with the 18 clock
pulses provided on the SCLK pin. The output data is valid on
both the rising and falling edge of the data clock.
D[17:10]
CS, RD
D[17:2]
A1
A0
HI-Z
HI-Z
Figure 35. 8-Bit and 16-Bit Parallel Interface
t
12
BYTE
HIGH
WORD
HIGH
t
12
BYTE
MID
t
WORD
12
BYTE
LOW
LOW
HI-Z
HI-Z
t
13
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MASTER SERIAL INTERFACE
Internal Clock
The AD7643 is configured to generate and provide the serial
data clock SCLK when the EXT/ INT pin is held low. The
AD7643 also generates a SYNC signal to indicate to the host
when the serial data is valid. The serial clock SCLK and the
SYNC signal can be inverted. Depending on the read during
convert input, RDC/SDIN, the data can be read after each
conversion or during the following conversion. Figure 36 and
Figure 37 show detailed timing diagrams of these two modes.
Usually, because the AD7643 is used with a fast throughput, the
master read during conversion mode is the most recommended
serial mode. In this mode, the serial clock and data toggle at
appropriate instants, minimizing potential feedthrough between
digital activity and critical conversion decisions. In this mode,
the SCLK period changes because the LSBs require more time
to settle and the SCLK is derived from the SAR conversion cycle.
In read after conversion mode, it should be noted that unlike
other modes, the BUSY signal returns low after the 18 data bits
are pulsed out and not at the end of the conversion phase,
resulting in a longer BUSY width. As a result, the maximum
throughput cannot be achieved in this mode.
In addition, in read after convert mode, the SCLK frequency
can be slowed down to accommodate different hosts using the
DIVSCLK[1:0] inputs. Refer to Table 4 for the SCLK timing
details when using these inputs.