EVAL-AD7643CBZ Analog Devices Inc, EVAL-AD7643CBZ Datasheet - Page 8

• Manufacturer Part Number: EVAL-AD7643CBZ
• Description: BOARD EVALUATION FOR AD7643
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7643CBZ

• Number Of Adc's: 1
• Number Of Bits: 18
• Sampling Rate (per Second): 1.25M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 65mW @ 1.25MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7643
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7643
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin
No.
1, 36,
41, 42
2, 44
3, 4
5
6, 7
8
9
10
11, 12
13
Mnemonic
AGND
AVDD
MODE[0:1]
D0/OB/2C
DGND
D1/A0
D2/A1
D3
D[4:5]
or DIVSCLK[0:1]
D6
or EXT/INT
Type
P
P
DI
DI/O
P
DI/O
DI/O
DO
DI/O
DI/O
1
Description
Analog Power Ground Pin.
Input Analog Power Pins. Nominally 2.5 V.
Data Output Interface Mode Selection.
Interface MODE#
0
1
2
3
When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus
and the data coding is straight binary. In all other modes, this pin allows the choice of straight
binary/twos complement. When OB/ 2C is high, the digital output is straight binary; when low,
the MSB is inverted resulting in a twos complement output from its internal shift register.
Connect to Digital Ground.
When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this
input pin controls the form in which data is output as shown in Table 7.
When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus.
When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus.
This pin is always an output, regardless of the interface mode.
When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read
after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the
internally generated serial clock that clocks the data output. In other serial modes, these pins are
high impedance outputs.
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus.
When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the
internally generated (master) or external (slave) serial data clock.
When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output.
When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal,
gated by CS, connected to the SCLK input.
NC = NO CONNECT
D4/DIVSCLK[0]
D5/DIVSCLK[1]
D0/OB/2C
MODE0
MODE1
AGND
DGND
DGND
AVDD
D1/A0
D2/A1
D3
10
11
12
1
2
3
4
5
6
7
8
9
13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44
Figure 4. Pin Configuration
PIN 1
IDENTIFIER
Rev. 0 | Page 8 of 28
(Not to Scale)
TOP VIEW
AD7643
MODE1
0
0
1
1
43 42 41 40
39 38 37
MODE0
1
0
1
0
36
35
34
33
32
31
30
29
28
27
26
25
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D17
D16
D15
D14
Description
18-bit interface
16-bit interface
8-bit (byte) interface
Serial interface