EVAL-AD7653CBZ Analog Devices Inc, EVAL-AD7653CBZ Datasheet - Page 23

• Manufacturer Part Number: EVAL-AD7653CBZ
• Description: BOARD EVALUATION FOR AD7653
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7653CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 92mW @ 666kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7653
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

External Discontinuous Clock Data Read After
Conversion
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave modes.
Figure 34
After a conversion is complete, indicated by BUSY returning
LOW, the conversion’s result can be read while both CS and RD
are LOW. Data is shifted out MSB first with 16 clock pulses and
is valid on the rising and falling edges of the clock.
Among the advantages of this method is the fact that conversion
performance is not degraded because there are no voltage
transients on the digital interface during the conversion process.
Another advantage is the ability to read the data at any speed up
to 40 MHz, which accommodates both the slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7653 provides a daisy-chain
feature using the RDC/SDIN pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when desired, as, for
instance, in isolated multiconverter applications.
The concatenation of two devices is shown in
Simultaneous sampling is possible by using a common CNVST
signal. It should be noted that the RDC/SDIN input is latched
on the edge of SCLK opposite the one used to shift out the data
on SDOUT. Thus, the MSB of the upstream converter follows
the LSB of the downstream converter on the next SCLK cycle.
CNVST IN
SCLK IN
CS IN
RDC/SDIN
(UPSTREAM)
AD7653
Figure 36. Two AD7653s in a Daisy-Chain Configuration
shows the detailed timing diagrams of this method.
BUSY
#2
CNVST
SDOUT
SCLK
CS
RDC/SDIN
(DOWNSTREAM)
AD7653
BUSY
#1
CNVST
SDOUT
SCLK
Figure 36
CS
02966-0-019
BUSY
OUT
DATA
OUT
.
Rev. A | Page 23 of 28
External Clock Data Read During Conversion
Figure 35 shows the detailed timing diagrams of this method.
During a conversion, while both CS and RD are both LOW, the
result of the previous conversion can be read. The data is shifted
out MSB first with 16 clock pulses, and is valid on both the
rising and falling edges of the clock. The 16 bits must be read
before the current conversion is complete; otherwise,
RDERROR is pulsed HIGH and can be used to interrupt the
host interface to prevent incomplete data reading. There is no
daisy-chain feature in this mode, and the RDC/SDIN input
should always be tied either HIGH or LOW.
To reduce performance degradation due to digital activity, a fast
discontinuous clock (at least 18 MHz when Impulse mode is
used, 25 MHz when Normal mode is used, or 40 MHz when
Warp mode is used) is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is also
possible to begin to read data after conversion and continue to
read the last bits after a new conversion has been initiated. This
allows the use of a slower clock speed like 14 MHz in Impulse
mode, 18 MHz in Normal mode, and 25 MHz in Warp mode.
AD7653