EVAL-AD7653CBZ Analog Devices Inc, EVAL-AD7653CBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD7653CBZ
• Description: BOARD EVALUATION FOR AD7653
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7653CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 1M
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 0 ~ 2.5 V
• Power (typ) @ Conditions: 92mW @ 666kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7653
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin No.
15
16
17
18
19
20
21
22
23
24
25–28
29
30
31
32
33
34
35
Mnemonic
D6 or
INVSCLK
D7 or
RDC/SDIN
OGND
OVDD
DVDD
DGND
D8 or
SDOUT
D9 or
SCLK
D10 or
SYNC
D11 or
RDERROR
D[12:15]
BUSY
DGND
RD
CS
RESET
PD
CNVST
Type
DI/O
DI/O
P
P
P
P
DO
DI/O
DO
DO
DO
DO
P
DI
DI
DI
DI
DI
1
Description
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active
in both master and slave modes.
When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus.
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on
DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data
is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
Input/Output Interface Digital Power Ground.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface
(5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground.
When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchro-
nized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the
conversion result, MSB first, from its internal shift register. The DATA format is determined by the
logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In
serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge
and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge
and valid on the next rising edge.
When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus.
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is
updated depends upon the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus.
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is
initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is
valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains
LOW while the SDOUT output is valid.
When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When
SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read
error flag. In slave mode, when a data read is started and not complete when the following
conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the
state of SER/PAR.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be
used as a data ready clock signal.
Must Be Tied to Digital Ground.
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock.
Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any,
is aborted. If not used, this pin could be tied to DGND.
Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are
inhibited after the current one is completed.
Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and
initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when
the acquisition phase (t
conversion is immediately started.
Rev. A | Page 9 of 28
8
) is complete, the internal sample/hold is put into the hold state and a
AD7653