EVAL-AD7951CBZ Analog Devices Inc, EVAL-AD7951CBZ Datasheet - Page 6

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EVAL-AD7951CBZ

Manufacturer Part Number
EVAL-AD7951CBZ
Description
BOARD EVALUATION FOR AD7951
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheets

Specifications of EVAL-AD7951CBZ

Number Of Adc's
1
Number Of Bits
14
Sampling Rate (per Second)
1M
Data Interface
Serial, Parallel
Inputs Per Adc
1 Differential
Input Range
±10 V
Power (typ) @ Conditions
235mW @ 1MSPS
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7951
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD7951
Parameter
SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES
(See Figure 42, Figure 43, and Figure 45)
1
2
3
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
DIVSCLK[0]
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.
In serial interface modes, the SDSYNC, SDSCLK, and SDOUT timings are defined with a maximum load C
In serial master read during convert mode. See Table 4 for serial master read after convert mode.
External SDCLK, SCCLK Setup Time
External SDCLK Active Edge to SDOUT Delay
SDIN/SCIN Setup Time
SDIN/SCIN Hold Time
External SDCLK/SCCLK Period
External SDCLK/SCCLK High
External SDCLK/SCCLK Low
Warp Mode
Normal Mode
Impulse Mode
TO OUTPUT
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT ARE DEFINED WITH A MAXIMUM LOAD
C
L
Figure 2. Load Circuit for Digital Interface Timing,
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
SDOUT, SYNC, and SCLK Outputs, C
PIN
60pF
C
L
1.6mA
500µA
I
I
OL
OH
1.4V
L
= 10 pF
2
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Symbol
t
t
t
t
t
t
t
t
t
18
19
19
20
21
22
23
24
28
Symbol
t
t
t
t
t
t
t
31
32
33
34
35
36
37
0
0
3
30
45
12
10
4
5
5
1.60
1.85
2.10
t
DELAY
0.8V
Min
5
2
5
5
25
10
10
L
of 10 pF; otherwise, the load is 60 pF maximum.
Figure 3. Voltage Reference Levels for Timing
0
1
20
60
90
30
25
20
8
7
2.35
2.60
2.85
2V
0.8V
Typ
1
0
20
120
180
60
55
20
35
35
3.75
4.00
4.25
2V
Max
18
1
1
20
240
360
120
115
20
90
90
6.75
7.00
7.25
t
2V
0.8V
DELAY
Unit
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
Unit
ns
ns
ns
ns
ns
ns
ns

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