AD9246-125EBZ Analog Devices Inc, AD9246-125EBZ Datasheet - Page 21

• Manufacturer Part Number: AD9246-125EBZ
• Description: BOARD EVAL FOR 125MSPS AD9246
• Manufacturer: Analog Devices Inc

Specifications of AD9246-125EBZ

• Design Resources: Using AD8376 to Drive Wide Bandwidth ADCs for High IF AC-Coupled Appls (CN0002) Driving AD9233/46/54 ADCs in AC-Coupled Baseband Appls (CN0051)
• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 458mW @ 125MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9246-125
• Silicon Manufacturer: Analog Devices
• Application Sub Type: ADC
• Kit Application Type: Data Converter
• Silicon Core Number: AD9246
• Kit Contents: Board
• Power Dissipation Pd: 458mW
• Input Channels Per Adc: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power-Down Mode
By asserting the PDWN pin high, the AD9246 is placed in
power-down mode. In this state, the ADC typically dissipates
1.8 mW. During power-down, the output drivers are placed in
a high impedance state. Reasserting the PDWN pin low returns
the AD9246 to its normal operational mode. This pin is both
1.8 V and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling
capacitors on REFT and REFB, it takes approximately 0.25 ms
to fully discharge the reference buffer decoupling capacitors and
0.35 ms to restore full operation.
Standby Mode
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).
DIGITAL OUTPUTS
The AD9246 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operat-
ing in the external pin mode (see Table 10).
Figure 54. AD9246-80 Power and Current vs. Clock Frequency f
290
275
260
245
230
215
0
IAVDD
20
CLOCK FREQUENCY (MSPS)
TOTAL POWER
40
IDRVDD
60
IN
80
= 30 MHz
150
120
90
60
30
0
Rev. A | Page 21 of 44
As detailed in the
Manual, the data format can be selected for either offset binary,
twos complement, or Gray code when using the SPI control.
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same pipeline
latency as the digital data.
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 55. OR remains high until the
analog input returns to within the input range, and another conver-
sion is completed. By logically AND’ing the OR bit with the MSB
and its complement, overrange high or underrange low conditions
can be detected. Table 11 is a truth table for the overrange/
underrange circuit in Figure 56, which uses NAND gates.
Table 11. Overrange/Underrange Truth Table
OR
0
0
1
1
Digital Output Enable Function (OEB)
The AD9246 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
OR DATA OUTPUTS
MSB
MSB
1
0
0
0
0
1
OR
Figure 55. OR Relation to Input Voltage and Output Data
MSB
0
1
0
1
11
11
11
00
00
00
1111
1111
1111
0000
0000
0000
Figure 56. Overrange/Underrange Logic
1111
1111
1111
0000
0000
0000
Analog Input Is:
Within range
Within range
Underrange
Overrange
Interfacing to High Speed ADCs via SPI User
1111
1111
1110
0001
0000
0000
–FS – 1/2 LSB
OR
–FS
–FS + 1/2 LSB
+FS – 1/2 LSB
+FS – 1 LSB
OVER = 1
UNDER = 1
+FS
AD9246