AD9245BCP-65EBZ Analog Devices Inc, AD9245BCP-65EBZ Datasheet
AD9245BCP-65EBZ
Specifications of AD9245BCP-65EBZ
Related parts for AD9245BCP-65EBZ
AD9245BCP-65EBZ Summary of contents
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FEATURES Single 3 V supply operation (2 3.6 V) SNR = 72.7 dBc to Nyquist SFDR = 83.0 dBc to Nyquist Low power 366 MSPS 300 MSPS 165 MSPS ...
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AD9245 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications.......................................................................... 5 Digital Specifications ................................................................... 7 Switching ...
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... Rev Page AD9245 AD9245BCP-65 Unit Max Min Typ Max 14 Bits 14 Bits ±1.75 ±0.50 ±1.75 % FSR ±3.25 ±0.50 ±6.90 % FSR ±1.00 ±0.50 ±1.00 LSB ±3.40 ±1.60 ±5.55 LSB ± ...
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... Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 4 for the equivalent analog input structure. 4 Measured at ac specification conditions without output drivers. 5 Standby power is measured with a dc input, CLK pin inactive (that is, set to AVDD or AGND). AD9245BCP-80 Min Typ 14 Guaranteed ± ...
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... Rev Page AD9245 AD9245BCP-65 Max Min Typ Max Unit 73.1 dBc dBc dBc 70.3 72.7 dBc 70.2 dBc 73.0 dBc dBc dBc 68.4 72 ...
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... MHz MHz MHz 100 MHz IN SPURIOUS-FREE DYNAMIC RANGE (SFDR 2.4 MHz MHz MHz 100 MHz IN AD9245BCP-80 Min Typ 71.1 73.3 72.7 70.5 71.7 70.2 70.7 73.2 72.5 69.9 71.2 69.6 11.5 11.9 11.8 11.3 11.5 11.3 −92.8 –87.6 −81.6 –79.0 76 ...
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... High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOH = 1.6 mA) Low Level Output Voltage (IOH = 50 μA) 1 AD9245BCP-80 performance measured with 1.0 V external reference. 2 Output voltage levels measured with 5 pF load on each output. AD9245BCP-20/AD9245BCP-40/AD9245BCP-65/AD9245BCP-80 Min Typ 2 ...
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... J 3 Wake-Up Time OUT-OF-RANGE RECOVERY TIME 1 For the AD9245BCP-65 and AD9245BCP-80 models only, with duty cycle stabilizer enabled. DCS function not applicable for AD9245BCP-20 and AD9245BCP-40 models. 2 Output delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load on each output. 3 Wake-up time is dependent on value of decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB. ...
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ABSOLUTE MAXIMUM RATINGS Table 7. Parameter With Respect to Min ELECTRICAL AVDD AGND –0.3 DRVDD DGND –0.3 AGND DGND –0.3 AVDD DRVDD –3 D13 DGND –0.3 CLK, MODE AGND –0.3 VIN+, VIN– AGND –0.3 VREF AGND –0.3 SENSE ...
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AD9245 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay ( The delay between the ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 9. Pin Function Descriptions Pin No. Mnemonic 1, 3 DNC 2 CLK 4 PDWN (LSB) to D13 (MSB) 15 DGND 16 DRVDD 21 OTR 22 MODE 23 ...
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AD9245 EQUIVALENT CIRCUITS AVDD VIN+, VIN– Figure 4. Equivalent Analog Input Circuit AVDD MODE Figure 5. Equivalent MODE Input Circuit 20kΩ Rev Page DRVDD D13-D0, OTR Figure 6. Equivalent Digital Output Circuit AVDD CLK, PDWN ...
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TYPICAL PERFORMANCE CHARACTERISTICS DUT = AD9245-80, AVDD = 3.0 V, DRVDD = 2.5 V, maximum sample rate, DCS disabled, T AIN = −0.5 dBFS, VREF = 1.0 V external, unless otherwise noted. 0 –10 –20 –30 –40 –50 –60 –70 ...
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AD9245 0 AIN = –6.5dBFS –10 SNR = 73.4dBFS SFDR = 86.0dBFS –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 FREQUENCY (MHz) Figure 14. Two-Tone 8K FFT @ 30 MHz and 31 ...
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INPUT FREQUENCY (MHz) Figure 20. SNR vs. Input Frequency 90 SFDR (DCS ON SFDR (DCS OFF ...
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AD9245 0 AIN = –0.5dBFS SNR = 72.7dBc –20 ENOB = 11.7 BITS SFDR = 81.3dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 26. AD9245-65 Single Tone 16K FFT @ 35 MHz 2.0 1.5 1.0 ...
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CODE Figure 32. AD9245-20 Typical INL 0 AIN = –0.5dBFS SNR = 73.4dBc –20 ENOB = 11.9 BITS SFDR = 95.0dBc –40 ...
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AD9245 THEORY OF OPERATION The AD9245 architecture consists of a front-end sample-and- hold amplifier (SHA) followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections consisting of a 4-bit first stage followed by eight 1.5-bit ...
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The SHA can be driven from a source that keeps the signal peaks within the allowable range for the selected reference voltage. The minimum and maximum common-mode input levels are defined as VREF = VCM MIN ...
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AD9245 JITTER CONSIDERATIONS High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (f ) due only to aperture jitter (t INPUT calculated with the following equation: ...
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As detailed in Table 11, the data format can be selected for either offset binary or twos complement. TIMING The AD9245 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs are available one propagation delay ...
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AD9245 VIN+ VIN– VREF + 10μF 0.1μF SELECT R2 LOGIC SENSE R1 0.5V AD9245 Figure 47. Programmable Reference Configuration EXTERNAL REFERENCE OPERATION The use of an external reference can be necessary to enhance the gain accuracy of the ADC or ...
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P2 5.0V VAMP VDL 2.5V GND 2.5V DRVDD GND AVDD 3.0V D10 17 D11 18 D12 19 D13 20 OTR 21 MODE 22 SENSE 23 VREF 24 Figure 49. LFCSP Evaluation Board Schematic—Analog Inputs and DUT Rev Page ...
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AD9245 Figure 50. LFCSP Evaluation Board Schematic—Digital Path Rev Page ...
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Figure 51. LFCSP Evaluation Board Schematic—Clock Input Rev Page AD9245 ...
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AD9245 Figure 52. LFCSP Evaluation Board Layout, Primary Side Figure 53. LFCSP Evaluation Board Layout, Secondary Side Figure 54. LFCSP Evaluation Board Layout, Ground Plane Figure 55. LFCSP Evaluation Board Layout, Power Plane Rev Page ...
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Figure 56. LFCSP Evaluation Board Layout, Primary Silkscreen Figure 57. LFCSP Evaluation Board Layout, Secondary Silkscreen Rev Page AD9245 ...
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... Chip Resistors 0603 Chip Resistors 0603 Chip Resistors 0603 Chip Resistors 0603 Resistor Packs R_742 ADT1-1WT AWT1-1T 74LVTH162374 CMOS Register TSSOP-48 AD9245BCP ADC (DUT) LFCSP-32 74VCX86M SOIC-14 AD92XXBCP/PCB PCB AD8351 Op Amp MSOP-8 M/A-COM Transformer ETC1-1-13 1-1 TX Chip Resistors 0603 Chip Resistors ...
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... AD9245BCPZRL7-40 –40°C to +85°C 2 AD9245BCPZ-20 –40°C to +85°C 2 AD9245BCPZRL7-20 –40°C to +85°C AD9245BCP-80EB AD9245BCP-65EB AD9245BCP-40EB AD9245BCP-20EB recommended that the exposed paddle be soldered to the ground plane for the LFCSP package. There is an increased reliability of the solder joints, and the maximum thermal capability of the package is achieved with the exposed paddle soldered to the customer board ...
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AD9245 NOTES Rev Page ...
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NOTES Rev Page AD9245 ...
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AD9245 NOTES © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03583–0–1/06(D) Rev Page ...