AD677-EB Analog Devices Inc, AD677-EB Datasheet
AD677-EB
Specifications of AD677-EB
Related parts for AD677-EB
AD677-EB Summary of contents
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... S/(N+D) Ratio, THD and IMD which are important in sig- nal processing applications. In addition, dc parameters are specified which are important in measurement applications. The AD677 operates from +5 V and 12 V supplies and typi- cally consumes 450 mW using reference (360 mW with 5 V reference) during conversion. The digital supply (V separated from the analog supplies (V tal crosstalk ...
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... Typ 2.0 –0 – – 0 – 0 1.0 kHz –0.05 dB, Bandwidth = 50 kHz unless otherwise indicated. All measurements referred –2– 10%) DD AD677K/B Min Typ Max –99 –95 –99 –95 – –101 –102 –98 1 160 5 – Max Units 0.8 V ...
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... REF * 2 6 100 0.5 0.5 0.5 14.5 14.5 3 360 450 to T after calibration at that temperature at nominal supplies. MAX –3– AD677 1O%) DD AD677K/B Max Min Typ Max +70 0 +70 +85 –40 + 1 0.5 0.5 0 REF REF * 2 50* 50* ...
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... AD677 TIMING SPECIFICATIONS Parameter 2, 3 Conversion Period 4 CLK Period Calibration Time Sampling Time 5 Last CLK to SAMPLE Delay SAMPLE Low SAMPLE to Busy Delay 1st CLK Delay 6 CLK Low 6 CLK High CLK to BUSY Delay CLK to SDATA Valid CLK to SCLK High SCLK Low SDATA to SCLK High ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD677 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... During calibration, SAMPLE should be held LOW. If HIGH during calibration, diagnostic information will appear on SDATA. DI Master Clock Input. The AD677 requires 17 clock pulses to execute a conversion. CLK is also used to derive SCLK. DO Serial Output Data Controlled by SCLK. ...
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... The IMD products are normalized input signal. APERTURE DELAY Aperture delay is the time required after SAMPLE pin is taken LOW for the internal sample-hold of the AD677 to open, thus holding the value APERTURE JITTER Aperture jitter is the variation in the aperture delay from sample to sample ...
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... In most applications sufficient to calibrate the AD677 only upon power-up, in which case care should be taken that the power supplies and voltage reference have stabilized first. If calibration is not performed, the AD677 may come un- known state, or performance could degrade to as low as 10 bits. CONVERSION CONTROL The AD677 is controlled by two signals: SAMPLE and CLK, as shown in Figure 2 ...
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... AD677 SAMPLE command from the system clock when a continuous convert mode is desirable. Pin 9 (2QC) pro- vides a 96 kHz sample rate for the AD677 when used with a 12.288 MHz system clock. Alternately, Pin 8 (2QD) could be used for a 48 kHz rate. ...
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... The input voltage range is determined by the value of the refer- ence voltage; in general, a reference voltage of n volts allows an input range of n volts. The AD677 is specified for a voltage reference between +5 V and + reference will typi- cally require support circuitry operated from 15 V supplies ...
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... C. A noise reduction capacitor reduces the broadband noise of the N AD586 output, thereby optimizing the overall performance of the AD677 recommended that high qual- ity tantalum capacitor and a 0.1 F capacitor be tied between the V input of the AD677 and ground to minimize the im- REF pedance on the reference ...
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... ACTUAL linearity performance. Figure 19 illustrates the DNL plot of a 6.02 typical AD677 at + histogram test is a statistical method for deriving an A/D converter’s differential nonlinearity. A ramp input is sampled by the ADC and a large number of conversions are taken and stored. Theoretically the codes would all be the same size and, therefore, have an equal number of occurrences ...
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... TFS0 Figure 10. ADSP-2101 Interface The SCLK pin of the ADSP-2101 SPORT0 provides the CLK input for the AD677. The clock should be programmed to be approximately 2 MHz to comply with AD677 specifications. To minimize digital feedthrough, the clock should be disabled (by setting Bit 14 in SPORT0 control register to 0) during data ac- quisition. Since the clock floats when disabled, a pulldown resis- tor – ...
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... AD677 100 1k 10k RIPPLE FREQUENCY – Hz Figure 15. AC Power Supply Rejection ( kSPS 0.13 V p-p SAMPLE RIPPLE 0 –30 –50 –70 –90 –110 –130 –150 FREQUENCY – kHz Figure 16. IMD Plot for f = 1008 Hz (fa), 1055 Hz (fb kSPS 106 THD, 5V 104 102 100 98 96 ...
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... BSC 0.0192 (0.49) 0.0125 (0.32) 0.0138 (0.35) 0.0091 (0.23) –15– AD677 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.0291 (0.74) ° ...
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