AD677-EB Analog Devices Inc, AD677-EB Datasheet - Page 4

• Manufacturer Part Number: AD677-EB
• Description: BOARD EVAL SAMPLING ADC AD677
• Manufacturer: Analog Devices Inc

Specifications of AD677-EB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: ±VREF
• Power (typ) @ Conditions: 450mW @ 100kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: AD677

AD677
TIMING SPECIFICATIONS
Parameter
Conversion Period
CLK Period
Calibration Time
Sampling Time
Last CLK to SAMPLE Delay
SAMPLE Low
SAMPLE to Busy Delay
1st CLK Delay
CLK Low
CLK High
CLK to BUSY Delay
CLK to SDATA Valid
CLK to SCLK High
SCLK Low
SDATA to SCLK High
CAL High Time
CAL to BUSY Delay
NOTES
1
2
3
5
6
4
See the “CONVERSION CONTROL” and “AUTOCALIBRATION” sections for detailed explanations of the above timing.
Depends upon external clock frequency; includes acquisition time and conversion time. The maximum conversion period is specified to account for the droop of the
t
If SAMPLE goes high before the 17th CLK pulse, the device will start sampling approximately 100 ns after the rising edge of the 17th CLK pulse.
t
580 ns is recommended for optimal accuracy over temperature (not necessary during calibration cycle).
internal sample/hold function. Operation at slower rates may degrade performance.
C
CH
= t
+ t
FCD
CL
+ 16
= t
6
6
CLK
4
and must be greater than 480 ns.
t
CLK
+ t
2, 3
LCS
.
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
(INPUT)
SAMPLE*
(INPUT)
(INPUT)
SDATA
5
BUSY
CLK
CAL
BUSY
SCLK
CLK
*
*
*
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
*
RECOMMEND THAT THESE SIGNALS BE HELD LOW EXCEPT WHEN EXPLICITY SHOWN HIGH.
SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
SHADED PORTIONS OF INPUT SIGNALS ARE OPTIONAL. FOR BEST PERFORMANCE, WE
(T
MIN
t
CALH
OLD BIT 16
t
FCD
t
t
t
S
FCD
t
to T
CALB
SB
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
C
CLK
CT
S
LCS
SL
SS
FCD
CL
CH
CB
CD
CSH
SCL
DSH
CALH
CALB
t
CLK
Figure 2. General Conversion Timing
MAX
t
, V
SL
t
1
CD
1
Figure 1. Calibration Timing
t
CC
CH
= +12 V
t
t
CH
CSH
2
2
t
t
CLK
MSB
SCL
t
CL
3
3
BIT
5%, V
–4–
2
t
CL
10
480
2
2.1
100
50
50
50
50
100
50
50
50
Min
t
t
DSH
CT
BIT
EE
13
15
= –12 V
85530
t
C
BIT
14
16
85531
BIT
15
5%, V
17
t
CB
Typ
30
180
100
180
80
80
15
85532
t
CB
DD
BIT
16
t
= +5 V
LCS
t
S
10%)
Max
1000
85532
75
300
175
300
50
1
REV. A
Units
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
s
s
s