CDB5530U Cirrus Logic Inc, CDB5530U Datasheet
CDB5530U
Specifications of CDB5530U
Related parts for CDB5530U
CDB5530U Summary of contents
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ADC Features & Description Chopper-stabilized Instrumentation Amplifier, 64X • 12 nV/√Hz @ 0.1 Hz (No 1/f noise) • 1200 pA Input Current Digital Gain Scaling up to 40x Delta-sigma Analog-to-digital Converter • Linearity Error: 0.0015% FS ...
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CHARACTERISTICS AND SPECIFICATIONS ................................................................. 4 ANALOG CHARACTERISTICS................................................................................ 4 TYPICAL NOISE-FREE RESOLUTION (BITS) ........................................................ DIGITAL CHARACTERISTICS .......................................................................... DIGITAL CHARACTERISTICS .......................................................................... 7 DYNAMIC CHARACTERISTICS .............................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................... 8 SWITCHING CHARACTERISTICS .......................................................................... 9 ...
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Figure 1. SDI Write Timing (Not to Scale)............................................................................... 10 Figure 2. SDO Read Timing (Not to Scale)............................................................................. 10 Figure 3. Front End Configuration........................................................................................... 11 Figure 4. Input Model for AIN+ and AIN- Pins......................................................................... 11 Figure 5. Measured Voltage Noise Density............................................................................. ...
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CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARCTERISTICS (VA+, VD ±5%; VREF VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate Sps; Bipolar Mode) (See Notes 1 and 2.) ...
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ANALOG CHARACTERISTICS (See Notes 1 and 2.) Parameter Analog Input Common Mode + Signal on AIN+ or AIN- CVF Current on AIN+ or AIN- Input Current Noise Open Circuit Detect Current Common Mode Rejection Input Capacitance Voltage Reference Input Range ...
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ANALOG CHARACTERISTICS (See Notes 1 and 2.) Power Supplies DC Power Supply Currents (Normal Mode) Power Consumption Power Supply Rejection 7. All outputs unloaded. All input CMOS levels. 8. Tested with 100 mV change on VA+ or VA-. TYPICAL NOISE-FREE ...
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V DIGITAL CHARACTERISTICS (VA+, VD ±5%; VA-, DGND = 0 V; See Notes 2 and 11.) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage A0 and A1, I Low-Level Output Voltage A0 and A1, ...
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DYNAMIC CHARACTERISTICS Parameter Modulator Sampling Rate Filter Settling Time to 1/2 LSB (full-scale Step Input) Single Conversion mode (Notes 12, 13, and 14) Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Sps 12. The ADCs ...
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SWITCHING CHARACTERISTICS (VA ±5%; VA- = -2.5V± VD+ = 3.0 V ±10 ±5%;DGND = 0 V; Levels: Logic Logic ...
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Figure 1. SDI Write Timing ...
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GENERAL DESCRIPTION The CS5530 is a ΔΣ Analog-to-Digital Converter (ADC) which uses charge-balance techniques to achieve 24-bit performance. The ADC is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and med- ical applications. ...
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Analog Input Span The full-scale input signal that the converter can dig- itize is a function of the reference voltage connected between the VREF+ and VREF- pins. The full-scale input span of the converter is ((VREF+) – (VREF-))/(64Y), where ...
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Write a logic 1 into the RS bit of the configuration regis- ter. This will reset the calibration registers and other logic (but not the ...
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Command Register Descriptions READ/WRITE OFFSET REGISTER D7(MSB R/W (Read/Write) 0 Write offset register. 1 Read offset register. READ/WRITE GAIN REGISTER D7(MSB R/W (Read/Write) 0 Write gain register. 1 Read gain register. READ/WRITE CONFIGURATION ...
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SYNC0 D7(MSB Function: End of the serial port re-initialization sequence. NULL D7(MSB Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. DS742F3 D5 D4 ...
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Serial Port Interface The CS5530’s serial interface consists of four con- trol lines: CS, SDI, SDO, SCLK. Figure 7 details the command and data word timing. CS, Chip Select, is the control line which enables access to the serial ...
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Reading/Writing On-Chip Registers The CS5530’s offset, gain, and configuration regis- ters are readable and writable while the conversion data register is read only. As shown in Figure 7, to write to a particular regis- ter the user must transmit ...
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Fine 1 φ Coarse 2 VREF C = 14pF ≤ MCLK VRS = ≤ V Figure 8. Input Reference Model when VRS = ...
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Configuration Register Description D31(MSB) D30 D29 D28 D27 PSS PDW RS RV D15 D14 D13 D12 D11 NU WR3 WR2 WR1 WR0 UP/BP OCD PSS (Power Save Select)[31] 0 Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode ...
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WR3-WR0 (Word Rate) [14:11] The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will scale linearly with the clock frequency used. The very first conversion using continuous conversion mode will last longer, ...
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Calibration Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5530 provides system calibration. Note: After the ADC is reset functional and can perform measurements without being calibrated (remember that ...
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Performing Calibrations To perform a calibration, the user must send a com- mand byte with its MSB=1, and the appropriate calibration bits (CC2-CC0) set to choose the type of calibration to be performed. The calibration will be performed using ...
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For maximum accuracy, calibrations should be per- formed for both offset and gain. When the device is used without calibration, the uncalibrated gain accuracy is about ±1 percent. Note that the gain from the offset register to the output is ...
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Table 1. Conversion Timing for Single Mode Clock Cycles (WR3-WR0) FRS = 0 0000 171448 ± 8 0001 335288 ± 8 0010 662968 ± 8 0011 1318328 ± 8 0100 2629048 ± 8 1000 7592 ± 8 1001 17848 ± ...
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Using Multiple ADCs Synchronously Some applications require synchronous data out- puts from multiple ADCs converting different ana- log channels. Multiple CS5530 devices can be synchronized in a single system by using the fol- lowing guidelines: 1) All of the ...
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Conversion Data Output Descriptions CS5530 (24-BIT CONVERSIONS) D31(MSB) D30 D29 D28 D27 MSB D15 D14 D13 D12 D11 Conversion Data Bits [31:8] These bits depict the latest output conversion. OF (Over-range ...
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Digital Filter The CS5530 has a linear phase digital filter which is programmed to achieve a range of output word rates (OWRs) as stated in the Configuration Regis- ter Description section. The ADC uses a Sinc ital filter to ...
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Clock Generator The CS5530 includes an on-chip inverting amplifi- er which can be connected with an external crystal to provide the master clock for the chip. Figure 17 illustrates the on-chip oscillator. It includes loading capacitors and a feedback ...
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V Analog Supply - Figure 18. CS5530 Configured with a Single +5 V Supply +2.5 V Analog Supply - -2.5 V Analog Supply Figure 19. CS5530 Configured with ±2.5 V Analog Supplies DS742F3 10 Ω 0.1 µ ...
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V Analog Supply - -3 V Analog Supply Figure 20. CS5530 Configured with ±3 V Analog Supplies 30 10 Ω 0.1 µ VA+ VD+ 18 OSC2 VREF+ 17 VREF- 3 OSC1 CS5530 4 ...
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Getting Started This A/D converter has several features. From a software programmer’s prospective, what should be done first? To begin, a 4.9152 MHz or 4.096 MHz crystal takes approximately start. To accommodate for this ...
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PIN DESCRIPTIONS DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT POSITIVE ANALOG POWER NEGATIVE ANALOG POWER LOGIC OUTPUT (ANALOG) LOGIC OUTPUT (ANALOG) MASTER CLOCK MASTER CLOCK Clock Generator OSC1; OSC2 – Master Clock An inverting ...
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Measurement and Reference Inputs AIN1+, AIN1- – Differential Analog Input Differential input pins into the device. VREF+, VREF- – Voltage Reference Input Fully differential inputs which establish the voltage reference for the on-chip modulator. C1, C2 – Amplifier Capacitor Inputs ...
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PACKAGE DRAWINGS 20 PIN SSOP PACKAGE DRAWING TOP VIEW DIM ∝ Notes: 1. “D” and “E1” are reference datums and do not included mold flash ...
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ORDERING INFORMATION Model Number Bits Channels Linearity Error (Max) Temperature Range CS5530- CS5530-ISZ ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp CS5530-IS 240 °C CS5530-ISZ 260 °C DS742F3 ±0.003% -40°C to +85°C ...
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Revision History REVISION DATE A1 OCT 2006 Advance Release A2 NOV 2006 Updated power consumption values. A3 NOV 2006 Updated noise density plot. A4 NOV 2006 Updated temperature range specification. F1 JAN 2007 Corrected input current 1200 ...