CDB5364 Cirrus Logic Inc, CDB5364 Datasheet - Page 3

• Manufacturer Part Number: CDB5364
• Description: EVALUATION BOARD FOR CS5364
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5364

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: I²C, SPI™
• Inputs Per Adc: 4 Differential
• Power (typ) @ Conditions: 365mW @ 192kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5364
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5364
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

DS625F4
TABLE OF CONTENTS
1. PIN DESCRIPTION ................................................................................................................................. 6
2. TYPICAL CONNECTION DIAGRAM
3. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 10
4. APPLICATIONS ................................................................................................................................... 19
5. REGISTER MAP ................................................................................................................................... 32
4.1 Power ............................................................................................................................................. 19
4.2 Control Port Mode and Stand-Alone Operation .............................................................................. 19
4.3 Master Clock Source ...................................................................................................................... 20
4.4 Master and Slave Operation ........................................................................................................... 21
4.5 Serial Audio Interface (SAI) Format ................................................................................................ 22
4.6 Speed Modes ................................................................................................................................. 23
4.7 Master and Slave Clock Frequencies ............................................................................................. 25
4.8 Reset .............................................................................................................................................. 27
4.9 Overflow Detection ......................................................................................................................... 27
4.10 Analog Connections ..................................................................................................................... 28
4.11 Optimizing Performance in TDM Mode ........................................................................................ 29
4.12 DC Offset Control ......................................................................................................................... 29
4.13 Control Port Operation .................................................................................................................. 30
5.1 Register Quick Reference ............................................................................................................. 32
5.2 00h (REVI) Chip ID Code & Revision Register ............................................................................... 32
RECOMMENDED OPERATING CONDITIONS ................................................................................. 10
ABSOLUTE RATINGS ....................................................................................................................... 10
SYSTEM CLOCKING ......................................................................................................................... 10
DC POWER ........................................................................................................................................ 11
LOGIC LEVELS ................................................................................................................................. 11
PSRR, VQ AND FILT+ CHARACTERISTICS .................................................................................... 11
ANALOG CHARACTERISTICS (COMMERCIAL) .............................................................................. 12
ANALOG CHARACTERISTICS (AUTOMOTIVE) ............................................................................... 13
DIGITAL FILTER CHARACTERISTICS ............................................................................................. 14
OVERFLOW TIMEOUT ...................................................................................................................... 14
SERIAL AUDIO INTERFACE - I²S/LJ TIMING ................................................................................... 15
SERIAL AUDIO INTERFACE - TDM TIMING ..................................................................................... 16
SWITCHING SPECIFICATIONS - CONTROL PORT - I²C TIMING ................................................... 17
SWITCHING SPECIFICATIONS - CONTROL PORT - SPI TIMING .................................................. 18
4.2.1 Stand-Alone Mode ................................................................................................................. 19
4.2.2 Control Port Mode ................................................................................................................. 19
4.3.1 On-Chip Crystal Oscillator Driver .......................................................................................... 20
4.3.2 Externally Generated Master Clock ....................................................................................... 20
4.4.1 Synchronization of Multiple Devices ...................................................................................... 21
4.5.1 I²S and LJ Format .................................................................................................................. 22
4.5.2 TDM Format .......................................................................................................................... 23
4.5.3 Configuring Serial Audio Interface Format ............................................................................ 23
4.6.1 Sample Rate Ranges ............................................................................................................ 23
4.6.2 Using M1 and M0 to Set Sampling Parameters .................................................................... 23
4.6.3 Master Mode Clock Dividers ................................................................................................. 24
4.6.4 Slave Mode Audio Clocking With Auto-Detect ...................................................................... 24
4.8.1 Power-Down Mode ................................................................................................................ 27
4.9.1 Overflow in Stand-Alone Mode .............................................................................................. 27
4.9.2 Overflow in Control Port Mode .............................................................................................. 27
4.13.1 SPI Mode ............................................................................................................................. 30
4.13.2 I²C Mode .............................................................................................................................. 31
................................................................................................... 9
CS5364
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