ADC12V170LFEB/NOPB National Semiconductor, ADC12V170LFEB/NOPB Datasheet - Page 3

• Manufacturer Part Number: ADC12V170LFEB/NOPB
• Description: BOARD EVAL FOR ADC12V170LF
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC12V170LFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 781mW @ 170MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12V170
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC12V170LFEB

ANALOG I/O
Pin Descriptions and Equivalent Circuits
Pin No.
43
45
44
46
3
4
8
7
CLK_SEL/DF
PD/Sleep
Symbol
V
V
V
V
V
V
REF
IN
IN
RM
RP
RN
−
+
Equivalent Circuit
3
Differential analog input pins. The differential full-scale input signal
level is two times the reference voltage with each input pin signal
centered on a common mode voltage, V
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close
to the pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between V
and a 10 µF capacitor should be placed in parallel. The 0.1
µFcapacitor should be as small as possible (preferably 0201).
V
use as a temperature stable 1.5V reference.
It is recommended to use V
voltage, V
This pin can be used as either the +1.0V internal reference voltage
output (internal reference operation) or as the external reference
voltage input (external reference operation).
To use the internal reference, V
with a 0.1 µF, low equivalent series inductance (ESL) capacitor. In
this mode, V
reference.
To use an external reference, overdrive this pin with a low noise
external reference voltage. The input impedance looking into this
pin is 9kΩ. Therefore, to overdrive this pin, the output impedance
of the external reference source should be << 9kΩ.
This pin should not be used to source or sink current.
The full scale differential input voltage range is 2 * V
This is a four-state pin controlling the input clock mode and output
data format.
CLK_SEL/DF = V
differential clock input. The output data format is 2's complement.
CLK_SEL/DF = (2/3)*V
differential clock input. The output data format is offset binary.
CLK_SEL/DF = (1/3)*V
clock input and CLK− should be tied to AGND. The output data
format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-ended clock
input and CLK− should be tied to AGND. The output data format is
offset binary.
This is a three-state input controlling Power Down and Sleep
modes.
PD/Sleep = V
only the reference voltage circuitry remains active and power
dissipation is reduced.
PD/Sleep = V
Power Down mode - it consumes more power but has a faster
recovery time.
PD/Sleep = AGND, Normal operation.
RP
and V
CM
RN
, for the differential analog inputs, V
REF
should not be loaded. V
A
A
/2, Sleep mode is enabled. Sleep mode is similar to
, Power Down is enabled. In the Power Down state
defaults as the output for the internal 1.0V
A
, CLK+ and CLK− are configured as a
RP
A
A
and V
, CLK+ and CLK− are configured as a
, CLK+ is configured as a single-ended
Description
RM
RN
to provide the common mode
REF
as close to the pins as possible,
should be decoupled to AGND
RM
may be loaded to 1mA for
CM
.
IN
+ and V
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REF
.
IN
−.