ADC12V170LFEB/NOPB National Semiconductor, ADC12V170LFEB/NOPB Datasheet - Page 9

• Manufacturer Part Number: ADC12V170LFEB/NOPB
• Description: BOARD EVAL FOR ADC12V170LF
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC12V170LFEB/NOPB

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 170M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 781mW @ 170MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC12V170
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC12V170LFEB

t
t
t
t
OD
DV
DNV
AD
Symbol
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: V
V
Typical values are for T
T
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: All voltages are measured with respect to GND = AGND = DGND = DRGND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supplies (that is, V
±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.
Note 4: The maximum allowable power dissipation is dictated by T
can be calculated using the formula P
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such
conditions should always be avoided.
Note 5: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω
Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7: The inputs are protected as shown below. Input voltage magnitudes above V
(Note 3). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.
Note 8: To guarantee accuracy, it is required that |V
Note 9: With the test condition for V
Note 10: Typical figures are at T
guaranteed.
Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative
full-scale.
Note 12: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Note 13: Optimum performance will be obtained by keeping the reference input in the 0.9V to 1.1V range. The LM4051CIM3-ADJ (SOT-23 package) is
recommended for external reference applications.
Note 14: This test parameter is guaranteed by design and characterization.
MIN
DR
= +1.8V, Internal V
≤
T
A
Maximum Clock Frequency
Minimum Clock Frequency
Clock High Time
Clock Low Time
Conversion Latency
Output Delay of CLK to DATA
Data Output Valid Time
Data Output Not Valid Time
Aperture Delay
Aperture Jitter
Power Down Recovery Time
Sleep Recovery Time
≤
T
MAX
. All other limits apply for T
REF
A
Parameter
= 25°C. Timing measurements are taken at 50% of the signal amplitude. Boldface limits apply for
A
= +1.0V, f
= 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not
REF
D,max
= +1.0V (2V
= (T
CLK
J,max
= 170 MHz, V
P-P
- T
A
–V
A
A
differential input), the 12-Bit LSB is 488.3 µV.
D
)/θ
= 25°C (Notes 7, 8, 9)
|
≤
JA
100 mV and separate bypass capacitors are used at each power supply pin.
. The values for maximum power dissipation listed above will be reached only when the device is
Relative to falling edge of CLK
Time output data is valid before the
output edge of DRDY (Note 14)
Time till output data is not valid after
the output edge of DRDY (Note
14)
0.1 µF to GND on pins 43, 44; 10 µF
and 0.1 µF between pins 43, 44; 0.1
µF and 10 µF to GND on pins 45, 46
0.1 µF to GND on pins 43, 44; 10 µF
and 0.1 µF between pins 43, 44; 0.1
µF and 10 µF to GND on pins 45, 46
J,max
CM
, the junction-to-ambient thermal resistance, (θ
= V
RM
Conditions
IN
9
, C
IN
= -1dBFS, AGND = DGND = DRGND = 0V, V
L
< AGND, or V
= 5 pF/pin, Single-Ended Clock Mode, Offset Binary Format.
A
30016811
or below GND will not damage this device, provided current is limited per
IN
> V
A
), the current at that pin should be limited to ±5 mA. The
(Note 10)
Typical
0.08
100
2.7
2.7
3.8
1.3
1.3
0.5
3.0
JA
), and the ambient temperature, (T
Limits
170
7.5
0.9
0.9
5
A
= V
Clock Cycles
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MHz (max)
D
MHz (min)
(Limits)
ns (min)
ns (min)
= +3.3V,
ps rms
Units
ms
ns
ns
ns
ns
µs
A
), and