HI5805EVAL1 Intersil, HI5805EVAL1 Datasheet - Page 10

• Manufacturer Part Number: HI5805EVAL1
• Description: EVALUATION PLATFORM HI5805
• Manufacturer: Intersil

Specifications of HI5805EVAL1

• Number Of Adc's: 1
• Number Of Bits: 12
• Sampling Rate (per Second): 5M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 4 Vpp
• Power (typ) @ Conditions: 300mW @ 5MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI5805
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Again, the difference between the two internal voltage
references is 2V. If V
4V
The converter will be at positive full scale when V
VDC + 2V (V
when V
case, V
significant change in ADC performance. The simplest way to
produce VDC is to use the V
HI5805.
The single ended analog input can be DC coupled (Figure
18) as long as the input is within the analog input common
mode voltage range.
The resistor, R, in Figure 18 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from V
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source will give better overall system
performance if it is first converted to differential before
driving the HI5805.
Digital I/O and Clock Requirements
The HI5805 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5805 to be driven by CMOS logic.
P- P
V
FIGURE 17. AC COUPLED SINGLE ENDED INPUT
FIGURE 18. DC COUPLED SINGLE ENDED INPUT
sinewave riding on a positive voltage equal to VDC .
V
IN
DC
IN
DC
+ is equal to VDC - 2V (V
could range between 2V and 3V without a
V
IN
IN
+ - V
V
DC
VDC
IN
IN
+ to V
IN
- = 2V) and will be at negative full scale
is a 4V
IN
- will help filter any high
R
DC
10
P-P
bias voltage output of the
sinewave, then V
C
IN
+ - V
V
V
IN
IN
IN
HI5805
-
V
+
V
HI5805
- = -2V). In this
IN
IN
-
+
IN
+ is at
IN
+ is a
HI5805
The digital CMOS outputs have a separate digital supply.
This allows the digital outputs to operate from a 3.0V to 5.0V
supply. When driving CMOS logic, the digital outputs will
swing to the rails. When driving standard TTL loads, the
digital outputs will meet standard TTL level requirements
even with a 3.0V supply.
In order to ensure rated performance of the HI5805, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5805 will only be guaranteed at
conversion rates above 0.5MSPS. This ensures proper
performance of the internal dynamic circuits.
Supply and Ground Considerations
The HI5805 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and
digital supplies and grounds. For best performance, the
supplies to the HI5805 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as
possible to the converter. If the part is powered off a single
supply then the analog supply and ground pins should be
isolated by ferrite beads from the digital supply and ground
pins.
Refer to the Application Note AN9214, “Using Intersil High
Speed A/D Converters” for additional considerations when
using high speed converters.
Static Performance Definitions
Offset Error (V
The midscale code transition should occur at a level
above half scale. Offset is defined as the deviation of the
actual code transition from this point.
Full-Scale Error (FSE)
The last code transition should occur for an analog input that
is
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Rejection Ratio (PSRR)
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
3
/
4
LSB below positive full scale with the offset error
OS
)
1
/
4
LSB