hi5805 Intersil Corporation, hi5805 Datasheet

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hi5805

Manufacturer Part Number
hi5805
Description
12-bit, 5 Msps A/d Converter
Manufacturer
Intersil Corporation
Datasheet

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Part Number:
hi5805BIB
Manufacturer:
HARRIS
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1 000
Part Number:
hi5805BIB
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HARRIS
Quantity:
20 000
Part Number:
hi5805BIBZ
Manufacturer:
INTERSIL
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20 000
12-Bit, 5MSPS A/D Converter
The HI5805 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Intersil’s HBC10 BiCMOS process. It
is designed for high speed, high resolution applications
where wide bandwidth and low power consumption are
essential.
The HI5805 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5805 has excellent dynamic
performance while consuming 300mW power at 5MSPS.
The 100MHz full power input bandwidth is ideal for
communication systems and document scanner
applications. Data output latches are provided which present
valid data to the output bus with a latency of 3 clock cycles.
The digital outputs have a separate supply pin which can be
powered from a 3.0V to 5.0V supply.
Ordering Information
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or
exceed the Pb-free requirements of IPC/JEDEC J STD-020.
HI5805BIB
HI5805BIBZ
(See Note)
HI5805EVAL1
NUMBER
PART
SAMPLE
5MSPS
5MSPS
RATE
RANGE (
-40 to 85
-40 to 85
TEMP.
25
®
1
o
C)
Data Sheet
28 Ld SOIC (W) M28.3
28 Ld SOIC (W)
(Pb-free)
Evaluation Board
PACKAGE
M28.3
DWG. #
PKG.
1-888-INTERSIL or 1-888-352-6832
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MSPS
• Low Power
• Internal Sample and Hold
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz
• Low Distortion
• Internal Voltage Reference
• TTL/CMOS Compatible Digital I/O
• Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 3.0V
• Pb-Free Available (RoHS Compliant)
Applications
• Digital Communication Systems
• Undersampling Digital IF
• Document Scanners
• Additional Reference Documents
Pinout
- AN9214 Using Intersil High Speed A/D Converters
- AN9707 Using the HI5805EVAL1 Evaluation Board
March 31, 2005
All other trademarks mentioned are the property of their respective owners.
|
DV
D
DV
D
V
Intersil (and design) is a registered trademark of Intersil Americas Inc.
AV
A
A
AV
ROUT
GND1
GND1
CLK
V
V
V
GND
V
GND
CC1
CC1
RIN
IN+
CC
DC
CC
IN-
Copyright Intersil Americas Inc. 2000, 2005. All Rights Reserved
10
11
12
13
14
1
2
3
4
5
6
7
8
9
TOP VIEW
HI5805
(SOIC)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D0
D1
D2
D3
D4
D5
DV
D
D6
D7
D8
D9
D10
D11
GND2
HI5805
CC2
FN3984.7

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hi5805 Summary of contents

Page 1

... The HI5805 is designed in a fully differential pipelined architecture with a front end differential-in-differential-out sample-and-hold (S/H). The HI5805 has excellent dynamic performance while consuming 300mW power at 5MSPS. ...

Page 2

... D9 (16) D10 D10 (MSB) (15) D11 D11 ( (8) IN CC1 V (10) ( CC1 V - (9) (22 CC2 0.1µF CLK (1) ( (14 0.1µF HI5805 CLOCK CLK V ROUT REF V RIN DV CC2 D11 (MSB) D10 (LSB) D GND2 A D BNC GND ...

Page 3

... Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Operating Conditions Temperature Range, HI5805BIB . . . . . . . . . . . . . . . . -40 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...

Page 4

... For a Valid Sample (Note 2) 5MSPS Clock 5MSPS Clock ± ± 3.5V, C RIN HI5805BIB (- MIN TYP MAX 200 - 3.5 - 7.8 - 450 - 0.4V - 1.6 -0 ...

Page 5

... N-th sampling period N-th holding period M-th stage digital output corresponding to N-th sampled input Final data output corresponding to N-th sampled input. N ANALOG INPUT CLOCK 1.5V INPUT DATA OUTPUT 5 HI5805 ...

Page 6

... INPUT FREQUENCY (MHz) FIGURE 5. SIGNAL TO NOISE RATIO (SNR) vs INPUT FREQUENCY INPUT FREQUENCY (MHz) FIGURE 7. SPURIOUS FREE DYNAMIC RANGE (SFDR) vs INPUT FREQUENCY 6 HI5805 70 = 5MSPS 100 FIGURE 4. SIGNAL TO NOISE AND DISTORTION (SINAD 5MSPS S o TEMPERATURE = 25 ...

Page 7

... TEMPERATURE AND INPUT FREQUENCY 306 304 302 300 298 296 -40 - TEMPERATURE ( FIGURE 11. POWER DISSIPATION vs TEMPERATURE 0 -20 -40 -60 -80 -100 -120 7 HI5805 (Continued) 3.525 2MHz 3.515 5MHz 10MHz 3.505 20MHz 3.495 50MHz 3.485 100MHz 3.475 FIGURE 10. INTERNAL VOLTAGE REFERENCE OUTPUT 70 ...

Page 8

... S external reference voltage is required are discharged to H connected to V the input signal is The HI5805 can be used with an external reference. The converter requires only one external reference voltage connected to the V The HI5805 is tested with V completing one H converter, two reference voltages of 1.3V and 3.3V are generated for a fully differential input signal range of ± ...

Page 9

... The voltages listed above represent the ideal center of each offset binary output code shown. Analog Input, Differential Connection The analog input to the HI5805 can be configured in various ways depending on the signal source and the required level of performance. A fully differential connection (Figure 15) will give the best performance for the converter ...

Page 10

... IN swing to the rails. When driving standard TTL loads, the digital outputs will meet standard TTL level requirements HI5805 even with a 3.0V supply. In order to ensure rated performance of the HI5805, the duty cycle of the clock should be held at 50% ±5%. It must also have low jitter and operate at standard TTL levels. ...

Page 11

... Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI5805. A low distortion sine wave is applied to the input coherently sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D ...

Page 12

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 12 HI5805 Aperture Delay ( ...

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