ADC11C170LFEBC National Semiconductor, ADC11C170LFEBC Datasheet - Page 4

• Manufacturer Part Number: ADC11C170LFEBC
• Description: BOARD EVAL FOR ADC11C170
• Manufacturer: National Semiconductor

Specifications of ADC11C170LFEBC

• Number Of Adc's: 1
• Number Of Bits: 11
• Sampling Rate (per Second): 170M
• Inputs Per Adc: 1 Differential
• Power (typ) @ Conditions: 747mW @ 170MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC11C170
• Lead Free Status / RoHS Status: Not applicable / Not applicable

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DIGITAL I/O
Pin No.
20-24,
27-32
17-19
11
12
33
34
8
7
CLK_SEL/DF
PD/Sleep
D0–D10
Symbol
OGND
DRDY
CLK+
CLK−
OVR
Equivalent Circuit
4
This is a four-state pin controlling the input clock mode and
output data format.
CLK_SEL/DF = V
differential clock input. The output data format is 2's
complement.
CLK_SEL/DF = (2/3)*V
a differential clock input. The output data format is offset
binary.
CLK_SEL/DF = (1/3)*V
ended clock input and CLK− should be tied to AGND. The
output data format is 2's complement.
CLK_SEL/DF = AGND, CLK+ is configured as a single-
ended clock input and CLK− should be tied to AGND. The
output data format is offset binary.
This is a three-state input controlling Power Down and Sleep
modes.
PD/Sleep = V
state only the reference voltage circuitry remains active and
power dissipation is reduced.
PD/Sleep = V
consumes more power than Power Down mode but has a
faster recovery time.
PD/Sleep = AGND, Normal operation.
The clock input pins can be configured to accept either a
single-ended or a differential clock input signal.
When the single-ended clock mode is selected through
CLK_SEL/DF (pin 8), connect the clock input signal to the
CLK+ pin and connect the CLK− pin to AGND.
When the differential clock mode is selected through
CLK_SEL/DF (pin 8), connect the positive and negative
clock inputs to the CLK+ and CLK− pins, respectively.
The analog input is sampled on the falling edge of the clock
input.
Digital data output pins that make up the 11-Bit conversion
result. D0 (pin 20) is the LSB, while D10 (pin 32) is the MSB
of the output word. Output levels are CMOS compatible.
Over-Range Indicator. This output is set HIGH when the
input amplitude exceeds the 11-Bit conversion range (0 to
2047).
Data Ready Strobe. This pin is used to clock the output data.
It has the same frequency as the sampling clock. One word
of data is output in each cycle of this signal. The rising edge
of this signal should be used to capture the output data.
Output GND, internally tied to GND through 5k ohm resistor
to provide pin compatibility with 12 or 14 bit ADCs.
A
A
, Power Down is enabled. In the Power Down
/2, Sleep mode is enabled. Sleep mode
A
, CLK+ and CLK− are configured as a
A
A
Description
, CLK+ and CLK− are configured as
, CLK+ is configured as a single-