MAX1162EVKIT Maxim Integrated Products, MAX1162EVKIT Datasheet - Page 12

• Manufacturer Part Number: MAX1162EVKIT
• Description: EVAL KIT FOR MAX1162
• Manufacturer: Maxim Integrated Products

Specifications of MAX1162EVKIT

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ VREF
• Power (typ) @ Conditions: 12.5mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1162, MAX1062
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3) Pull CS high at or after the 24th falling clock edge. If
4) With CS high, wait at least 50ns (t
Data can be output in three 8-bit sequences or continu-
ously. The bytes contain the results of the conversion
padded with eight leading zeros before the MSB. If the
serial clock has not been idled after the sub-bits (S1
and S0) and CS has been kept low, DOUT sends trail-
ing zeros.
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
Figure 10a. SPI Connections
Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA =0)
12
format. Observe the SCLK to DOUT valid timing
characteristic. Clock data into the µP on SCLK’s ris-
ing edge.
CS remains low, trailing zeros are clocked out after
the 2 sub-bits, S1 and S0.
ing a new conversion by pulling CS low. A conver-
sion can be aborted by pulling CS high before the
conversion ends. Wait at least 50ns before starting a
new conversion.
*WHEN CS IS HIGH, DOUT = HIGH-Z
DOUT*
SCLK
______________________________________________________________________________________
CS
SPI
MISO
SCK
I/O
SS
0
1
V
DD
0
0
1ST BYTE READ
0
CS
SCLK
DOUT
4
CSW
MAX1062
0
) before start-
D5
0
6
D4
0
0
D3
8
3RD BYTE READ
D2
20
When using the SPI (Figure 10a) or MICROWIRE
(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.
Conversion begins with a falling edge on CS (Figure
10c). Three consecutive 8-bit readings are necessary
to obtain the entire 14-bit result from the ADC. DOUT
data transitions on the serial clock’s falling edge. The
first 8-bit data stream contains all leading zeros. The
second 8-bit data stream contains the MSB through D6.
The third 8-bit data stream contains D5 through D0 fol-
lowed by S1 and S0.
Using the high-speed QSPI interface with CPOL = 0
and CPHA = 0, the MAX1062 supports a maximum
f
nected to a QSPI master and Figure 11b shows the
associated interface timing.
Figure 10b. MICROWIRE Connections
SCLK
D1
LSB
D0
of 4.8MHz. Figure 11a shows the MAX1062 con-
MICROWIRE
D13
MSB
S1
D12
S0
SPI and MICROWIRE Interfaces
I/O
SK
24
SI
D11
HIGH-Z
D10
2ND BYTE READ
12
D9
D8
CS
SCLK
DOUT
QSPI Interface
D7
MAX1068
MAX1067
D6
16
D5