MAX1162EVKIT Maxim Integrated Products, MAX1162EVKIT Datasheet - Page 7

• Manufacturer Part Number: MAX1162EVKIT
• Description: EVAL KIT FOR MAX1162
• Manufacturer: Maxim Integrated Products

Specifications of MAX1162EVKIT

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 200k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ VREF
• Power (typ) @ Conditions: 12.5mW @ 200kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: MAX1162, MAX1062
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1062 includes an input track-and-hold (T/H)
and successive-approximation register (SAR) circuitry
to convert an analog input signal to a digital 14-bit out-
put. Figure 4 shows the MAX1062 in its simplest config-
uration. The serial interface requires only three digital
lines (SCLK, CS, and DOUT) and provides an easy
interface to microprocessors (µPs).
The MAX1062 has two power modes: normal and shut-
down. Driving CS high places the MAX1062 in shut-
down, reducing the supply current to 0.1µA (typ), while
pulling CS low places the MAX1062 in normal operating
mode. Falling edges on CS initiate conversions that are
driven by SCLK. The conversion result is available at
DOUT in unipolar serial format. The serial data stream
consists of eight zeros followed by the data bits (MSB
first). Figure 3 shows the interface-timing diagram.
Figure 5 illustrates the input sampling architecture of
the ADC. The voltage applied at REF sets the full-scale
input voltage.
In track mode, the analog signal is acquired on the
internal hold capacitor. In hold mode, the T/H switches
open and the capacitive DAC samples the analog
input.
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
PIN
3, 9
10
1
2
4
5
6
7
8
NAME
DGND
AGND
DOUT
DV
AV
SCLK
_______________________________________________________________________________________
REF
AIN
CS
DD
DD
Detailed Description
External Reference Voltage Input. Sets the analog voltage range. Bypass to AGND with a 4.7µF
capacitor.
Analog +5V Supply Voltage. Bypass to AGND (pin 3) with a 0.1µF capacitor.
Analog Ground. Connect pins 3 and 9 together. Place star ground at pin 3.
Active Low Chip Select Input. Forcing CS high places the MAX1062 in shutdown with a typical
current of 0.1µA. A high-to-low transition on CS activates normal operating mode and initiates a
conversion.
Serial Clock Input. SCLK drives the conversion process and clocks out data at data rates up to
4.8MHz.
Serial Data Output. Data changes state on SCLK’s falling edge. DOUT is high impedance when CS
is high.
Digital Ground
Digital Supply Voltage. Bypass to DGND with a 0.1µF capacitor.
Analog Input
Track-and-Hold (T/H)
Analog Input
During the acquisition, the analog input (AIN) charges
capacitor C
falling edge of the sixth clock cycle (Figure 6). At this
instant, the T/H switches open. The retained charge on
C
In hold mode, the capacitive digital-to-analog converter
(DAC) adjusts during the remainder of the conversion
cycle to restore node ZERO to zero within the limits of
14-bit resolution. At the end of the conversion, force CS
high and then low to reset the input side of the C
switches back to AIN, and charge C
signal again.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens and more time must be
allowed between conversions. The acquisition time
(t
the signal. Use the following formula to calculate acqui-
sition time:
where R
impedance, and t
source impedance less than 1kΩ does not significantly
affect the ADC’s performance.
To improve the input signal bandwidth under AC condi-
tions, drive AIN with a wideband buffer (>4MHz) that
can drive the ADC’s input capacitance and settle
quickly.
ACQ
DAC
) is the maximum time the device takes to acquire
FUNCTION
represents a sample of the input.
IN
DAC
= 800Ω, R
t
ACQ
. The acquisition interval ends on the
= 11(R
ACQ
S
is never less than 1.1µs. A
= the input signal’s source
S
+ R
Pin Description
IN
) x 35pF
DAC
to the input
DAC
7