DK86065-2 Fujitsu Semiconductor America Inc, DK86065-2 Datasheet - Page 33

• Manufacturer Part Number: DK86065-2
• Description: KIT EVAL 16BIT DAC FOR MB86065
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86065-2

• Number Of Dac's: 1
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86065
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1011

September 2007 Version 1.01
FME/MS/DAC80S/DS/5344
MB86065 14-bit 1+GSa/s DAC
4.6
Copyright © 2004-2007 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
Clock Input
Square Wave
Sinusoidal (recommended)
Clock Outputs (LVDS)
Loop Clock (LVDS)
T
1. Requires appropriate DAC CORE CLOCK DELAY settings. Refer to Sections 1.1.2 & 1.1.3.
2. Ensure clock input symmetry to obtain best performance. Deviation from this will increase Fclk related images.
3. Power into 100R termination.
4. Also applies to Loop Clock Output.
5. R
6. Assumes ‘clkoutx_clk_dly’ is set to its minimum (default) setting.
7. At 500MHz. Assumes ‘clkoutx_clk_dly’ is set to its minimum (default) setting.
8. Assumes ‘loop_clk_dly’ is set to its minimum (default) setting.
A
Maximum clock frequency
Clock frequency for 1+GSa/s mode
Low time
High time
Slew rate for minimum wide-band jitter
Clock input duty cycle
Low-level input voltage
High-level input voltage
Common mode input voltage
Signal level (f
Common mode output voltage
Differential output voltage
Delay, CLKIN to CLKx_OUT
Jitter added, CLKIN to CLKx_OUT (rms)
Jitter added, CLKIN to CLKx_OUT (pk-pk)
Delay, LPCLK_IN to LPCLK_OUT
(min) to T
T
= 50
Clock Specifications
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
A
(max), AVD33 = +3.3V, AVSS = 0V, DVDD = +1.8V, DVSS = 0V
double 100 termination) across the LVDS Q and Q signals.
Clk
= 312MHz)
Parameter
Notes
4 & 5
1
2
3
4
6
7
7
8
Symbol
t
LPLCLK
t
V
V
V
CLKO
F
V
t
V
t
t
LO
SL
HI
CM
CM
OD
clk
IH
IL
Production
V
200mV
DVSS
0.95
0.95
Min.
500
500
320
0.5
0.9
0.5
-2
-
Ratings
Typ.
600
575
350
1.2
1.1
2.9
1.3
50
30
1
1
4
5
V
200mV
DVDD
Max.
650
+10
550
1.8
1.2
+
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Units
MHz
MHz
V/ns
dBm
mV
ns
ns
ns
ns
ps
ps
%
V
V
V
V