DK86064-2 Fujitsu Semiconductor America Inc, DK86064-2 Datasheet - Page 7

• Manufacturer Part Number: DK86064-2
• Description: KIT DEB DUAL 14BIT DAC MB86064
• Manufacturer: Fujitsu Semiconductor America Inc

Specifications of DK86064-2

• Number Of Dac's: 2
• Number Of Bits: 14
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MB86064
• For Use With: 865-1111 - DAC DK FPGA ADAPTER BOARD865-1012 - KIT DEV DUAL 14BIT MB86064 SMA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1010

October 2005 Version 1.2
FME/MS/DAC80/DS/4972
MB86064 Dual 14-bit 1GSa/s DAC
1.1.4 Clock Outputs
Two clock outputs, CLK1_OUT and CLK2_OUT, are provided to enable synchronisation of data
generating devices to the DAC. The reference clock used by the Clock Output block can be disabled
if required. See Table 3.
The output frequency can be individually selected as the input clock divided-by-1, 2, 4 or 8.
Configuration is through register WMM CONFIG, bits clkout1_cfg and clkout2_cfg. See Table 4.
Also, programmable delay stages are provided in both CLK1_OUT and CLK2_OUT outputs. These
clock output delays are programmed through register SYSTEM CLOCK DELAYS clkout1_clk_dly
and clkout2_clk_dly. See Table 5 and Table 6.
Copyright © 2004-2005 Fujitsu Microelectronics Europe GmbH
Disclaimer : The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before
SYSTEM MISC
clkout1_clk_dly
Table 4: Waveform Memory Module Register: WMM CONFIG [0x00] (Part 1 of 2)
clkout1_cfg
clkout2_cfg
ordering.The information and circuit diagrams in this document are presented “as is”, no license is granted by implication or otherwise.
Table 5: DAC Core Register: SYSTEM CLOCK DELAYS [0x1C1] (Part 2 of 4)
Label
Label
(bit)
0
Table 3: DAC Core Register: SYSTEM MISC [0x1C4] (Part 1 of 3)
en_ref_clk
3
0
0
1
1
7
0
1
:
Label
Reg Bits
Reg Bits
2
0
1
0
1
6
0
1
:
1
5
0
0
1
1
0
1
:
Reference clock control
0 = Enabled (default), 1 = Disabled
0
4
0
1
0
1
0
1
:
Clock output 1 = clock input (default)
Clock output 1 = clock input divided by 2
Clock output 1 = clock input divided by 4
Clock output 1 = clock input divided by 8
Clock output 2 = clock input (default)
Clock output 2 = clock input divided by 2
Clock output 2 = clock input divided by 4
Clock output 2 = clock input divided by 8
Minimum (default)
Maximum
Divided Clock Output Configuration
(0 - 1.5ns, 100ps steps)
Clock Output Delay
Function
Production
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