HI5731-EVS Intersil, HI5731-EVS Datasheet

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HI5731-EVS

Manufacturer Part Number
HI5731-EVS
Description
EVALUATION PLATFORM SOIC HI5731
Manufacturer
Intersil
Datasheets

Specifications of HI5731-EVS

Number Of Dac's
1
Number Of Bits
12
Outputs And Type
1, Differential
Sampling Rate (per Second)
100M
Data Interface
Parallel
Settling Time
20ns
Dac Type
Current
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
HI5731
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
12-Bit, 100MSPS, High Speed D/A
Converter
The HI5731 is a 12-bit, 100MSPS, D/A converter which is
implemented in the Intersil BiCMOS 10V (HBC-10) process.
Operating from +5V and -5.2V, the converter provides
-20.48mA of full scale output current and includes an input
data register and bandgap voltage reference. Low glitch
energy and excellent frequency domain performance are
achieved using a segmented architecture. The digital inputs
are TTL/CMOS compatible and translated internally to ECL.
All internal logic is implemented in ECL to achieve high
switching speed with low noise. The addition of laser
trimming assures 12-bit linearity is maintained along the
entire transfer curve.
Ordering Information
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020C.
HI5731BIP
HI5731BIPZ
(See Note)
HI5731BIB
HI5731BIB-T
HI5731BIBZ
(See Note)
HI5731-EVS
PART NUMBER
28 Ld SOIC Tape and Reel
RANGE (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TEMP.
25
®
1
28 Ld PDIP
28 Ld PDIP
(Pb-free)
28 Ld SOIC
28 Ld SOIC
(Pb-free)
Evaluation Board (SOIC)
PACKAGE
Data Sheet
E28.6
E28.6
M28.3
M28.3
M28.3
PKG. DWG.
#
1-888-INTERSIL or 321-724-7143
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
Features
• Pb-free Available as an Option
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . 100MSPS
• Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650mW
• Integral Linearity Error . . . . . . . . . . . . . . . . . . . . 0.75 LSB
• Low Glitch Energy . . . . . . . . . . . . . . . . . . . . . . . . . 3.0pV-s
• TTL/CMOS Compatible Inputs
• Improved Hold Time . . . . . . . . . . . . . . . . . . . . . . . . 0.25ns
• Excellent Spurious Free Dynamic Range
Applications
• Cellular Base Stations
• GSM Base Stations
• Wireless Communications
• Direct Digital Frequency Synthesis
• Signal Reconstruction
• Test Equipment
• High Resolution Imaging Systems
• Arbitrary Waveform Generators
Pinout
September 15, 2004
D11 (MSB)
D0 (LSB)
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
D10
NC
NC
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
D9
D8
D7
D6
D5
D4
D3
D2
D1
10
11
12
13
14
1
2
3
4
5
6
7
8
9
(PDIP, SOIC)
TOP VIEW
HI5731
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DGND
AGND
REF OUT
CTRL OUT
CTRL IN
R
AV
I
I
ARTN
DV
DGND
DV
CLOCK
OUT
OUT
SET
HI5731
EE
EE
CC
FN4070.9

Related parts for HI5731-EVS

HI5731-EVS Summary of contents

Page 1

... Ld SOIC Tape and Reel HI5731BIBZ - SOIC (See Note) (Pb-free) HI5731-EVS 25 Evaluation Board (SOIC) NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C ...

Page 2

... Typical Application Circuit 50Ω 0.1µF Functional Block Diagram (LSB 12-BIT D5 MASTER REGISTER D10 (MSB) D11 CLK AV AGND DV DGND HI5731 +5V HI5731 0.01µF DV (16) CC D11 (MSB) (1) D11 D10 (2) D10 (24) CTRL IN D9 (3) D9 (25) CTRL OUT D8 ( (5) D7 (26) REF OUT (7) (21) I OUT (9) D2 ...

Page 3

... Spurious Free Dynamic Range within a Window (Note 3) 3 HI5731 Thermal Information Thermal Resistance (Typical, Note 1) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to -0.5V Maximum Junction Temperature CC HI5731BIx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Maximum Storage Temperature Range . . . . . . . . . . -65 Maximum Lead Temperature (Soldering 10s .300 (SOIC - Lead Tips Only -4.94 to -5.46V +4.75 to +5.25V, V ...

Page 4

... R = 50Ω, 100mV Sine Wave, to -3dB Loss (Note 3) (Note 4) (Note 4) (Note 4) (Note 4) (Note 3) See Figure 1 (Note 3) See Figure 1 (Note 3) See Figure 1 (Note 3) See Figure 1 (Note 3) (Note 4) (Note 4) (Note 4) (Note 4) ±5%, V ± Internal REF HI5731BI - MIN TYP MAX - -1.27 -1.23 -1.17 - 175 ...

Page 5

... SETT t PD FIGURE 1. FULL SCALE SETTLING TIME DIAGRAM t CLK t SU D11-D0 I OUT t PD FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 5 HI5731 50% 1 ± / LSB ERROR BAND 2 FIGURE 2. PEAK GLITCH AREA (SINGLET) MEASUREMENT t PW1 PW2 HLD HLD ...

Page 6

... TEMPERATURE 1.5 0.5 -0.5 1.5 0 600 1200 1800 2400 CODE FIGURE 6. TYPICAL INL -40 - TEMPERATURE FIGURE 8. OFFSET CURRENT OVER TEMPERATURE 6 HI5731 -1.21 -1.23 -1.25 -1.27 -1. -50 FIGURE 5. TYPICAL REFERENCE VOLTAGE OVER 0.8 0.4 0.0 -0.4 -0.8 3000 3600 4200 ATTEN 20dB RL -10.0dBm 100 CENTER 1 ...

Page 7

... RL -10.0dBm 10dB CENTER 10.100MHz FIGURE 12. SPURIOUS FREE DYNAMIC RANGE = -81.67dBc ATTEN 20dB RL -10.0dBm 10dB CENTER 2.027MHz FIGURE 14. SPURIOUS FREE DYNAMIC RANGE = -85.60dBc 7 HI5731 (Continued) ∆MKR -76.16dB ATTEN 20dB -53kHz RL -10.0dBm f = 20MSPS SPAN 2.000MHz CENTER 16.00MHz FIGURE 11. SPURIOUS FREE DYNAMIC RANGE = 75.17dBc ∆ ...

Page 8

... CENTER 10.133MHz FIGURE 16. SPURIOUS FREE DYNAMIC RANGE = 80.5dBc ATTEN 20dB RL -10.0dBm 10dB START FREQUENCY 500kHz STOP FREQUENCY 20MHz FIGURE 18. SPURIOUS FREE DYNAMIC RANGE = 71.16dBc HI5731 (Continued) ∆MKR -80.50dB ATTEN 20dB -807kHz RL -10.0dBm f = 100MSPS SPAN 2.000MHz CENTER 26.637MHz FIGURE 17. SPURIOUS FREE DYNAMIC RANGE = 72.17dBc ∆ ...

Page 9

... Can sink up to 125µ overdriven by an external reference capable of delivering up to 2mA. Detailed Description The HI5731 is a 12-bit, current out D/A converter. The DAC can convert at 100MSPS and runs on +5V and -5.2V supplies. The architecture is an R/2R and segmented switching current cell arrangement to reduce glitch ...

Page 10

... CC decoupled with a 0.1µF capacitor. Reference The internal reference of the HI5731 is a -1.23V (typical) bandgap voltage reference with 175µV/ drift (typical). The internal reference is connected to the Control Amplifier which in turn drives the segmented current cells. Reference Out (REF OUT) is internally connected to the Control Amplifier ...

Page 11

... Settling Time The settling time of the HI5731 is measured as the time it takes for the output of the DAC to settle to within a ± error band of its final value during a full scale (code 0000... to 1111.... or 1111... to 0000...) transition. All claims made by Intersil with respect to the settling time performance of the HI5731 have been fully verified by the National Institute of Standards and Technology (NIST) and are fully traceable ...

Page 12

... Interfacing to the HSP45106 NCO-16 The HSP45106 is a 16-bit, Numerically Controlled Oscillator (NCO). The HSP45106 can be used to generate various modulation schemes for Direct Digital Synthesis (DDS) applications. Figure 28 shows how to interface an HI5731 to the HSP45106. Interfacing to the HSP45102 NCO-12 The HSP45102 is a 12-bit, Numerically Controlled Oscillator (NCO) ...

Page 13

... CLK BASEBAND BIT ENCODER STREAM V CC CONTROLLER FIGURE 28. MODULATOR USING THE HI5731 AND THE HSP45106 16-BIT NCO 13 HI5731 U2 K9 CLK C11 MOD2 B11 MOD1 C10 MOD0 A11 PMSEL DACSTRB F10 K3 SIN15 ENPOREG F9 L2 SIN14 ENOFREG F11 L3 SIN13 ENCFREG H11 L4 SIN12 ...

Page 14

... CLK I BASEBAND BIT ENCODER Q STREAM CONTROL BUS CONTROLLER FIGURE 29. PSK MODULATOR USING THE HI5731 AND THE HSP45102 12-BIT NCO 14 HI5731 CLK 6 1 OUT11 OUT10 OUT9 OUT8 LOAD# OUT7 1 6 OUT6 TXFR# OUT5 OUT4 ENPHAC OUT3 OUT2 SEL_L/ OUT1 23 12 OUT0 ...

Page 15

... Thickness 17k Metallization Mask Layout HI5731 PASSIVATION Type: Sandwich Passivation Undoped Silicon Glass (USG) + Nitride Thickness: USG - 8k SUBSTRATE POTENTIAL (POWERED UP) V EED HI5731 D9 D10 D11 DGND CLK DV DGND CC Å Å , Nitride - 4.2k Å Å Total 12. CTRL OUT CTRL IN R SET AV EE ...

Page 16

... B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 16 HI5731 E28.6 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE SYMBOL E A2 ...

Page 17

... Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 17 HI5731 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE ...

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