LP55281RLEV National Semiconductor, LP55281RLEV Datasheet - Page 21

• Manufacturer Part Number: LP55281RLEV
• Description: BOARD EVAL FOR LP5528 RGB DRIVER
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP55281RLEV

• Current - Output / Channel: 400mA
• Outputs And Type: 12, Non-Isolated
• Voltage - Output: 5.3V
• Features: USB Interface
• Voltage - Input: 2.7 ~ 5.5V
• Utilized Ic / Part: LP55281
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
Interface Bus Overview
The I
cess to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bidirec-
tional communications between the IC's connected to the bus.
The two interface lines are the Serial Data Line (SDA) and the
Serial Clock Line (SCL). These lines should be connected to
a positive supply, via a pull-up resistor and remain HIGH even
when the bus is idle.
For every device on the bus is assigned a unique address and
it acts as a Master or a Slave, depending on whether it gen-
erates or receives the serial clock (SCL). When LP55281 is
connected in parallel with other I
LP55281 supply voltages V
tive. Supplies are required to make sure that the LP55281
does not disturb the SDA and SCL lines.
Data Transactions
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL). Con-
sequently, throughout the clock's high period, the data should
remain stable. Any changes on the SDA line during the high
states of the SCL and in the middle of the transaction, aborts
the current transaction. New data should be sent during the
low SCL state. This protocol permits a single data line to
transfer both command/control information and data using the
synchronous serial clock.
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software) and a Stop
Condition to terminate the transaction. Every byte written to
the SDA bus must be 8 bits long and is transferred with the
most significant bit first. After each byte, an Acknowledge sig-
nal must follow. The following sections provide further details
of this process.
2
C COMPATIBLE SERIAL BUS INTERFACE
2
C compatible synchronous serial interface provides ac-
Data Validity
DD1
, V
2
DD2
C compatible devices, the
and V
DDIO
must be ac-
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The Master device on the bus always generates the Start and
Stop Conditions (control codes). After a Start Condition is
generated, the bus is considered busy and it retains this sta-
tus until a certain time after a Stop Condition is generated. A
high-to-low transition of the data line (SDA), while the clock
(SCL) is high, indicates a Start Condition. A low-to-high tran-
sition of the SDA line, while the SCL is high, indicates a Stop
Condition
In addition to the first Start Condition, a repeated Start Con-
dition can be generated in the middle of a transaction. This
allows another device to be accessed or a register read cycle.
Acknowledge Cycle
The Acknowledge Cycle consists of two signals: the acknowl-
edge clock pulse the master sends with each byte transferred,
and the acknowledge signal sent by the receiving device.
The master generates the acknowledge clock pulse on the
ninth clock pulse of the byte transfer. The transmitter releases
the SDA line (permits it to go high) to allow the receiver to
send the acknowledge signal. The receiver must pull down
the SDA line during the acknowledge clock pulse and ensure
that SDA remains low during the high period of the clock
pulse, thus signaling the correct reception of the last data byte
and its readiness to receive the next byte.
"ACKNOWLEDGE AFTER EVERY BYTE" Rule
The Master generates an acknowledge clock pulse after each
byte transfer. The receiver sends an acknowledge signal after
every byte received.
There is one exception to the "acknowledge after every byte"
rule. When the master is the receiver, it must indicate to the
transmitter an end of data by not-acknowledging ("negative
acknowledge") the last byte clocked out of the slave. This
Start and Stop Conditions
Acknowledge Signal
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