EVK1060A Atmel, EVK1060A Datasheet

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Features • Configurations: – Can be configured as a combination of keys and input/output lines • Number of Keys: – • Number of I/O Lines: – 7, configurable for input or output, with PWM control for LED ...

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Pinout and Schematic 1.1 Pinout Configuration 1.2 Pin Descriptions Table 1-1. Pin AT42QT1060 ...

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Table 1-1. Pin 9505E–AT42–02/09 Pin Listing (Continued) Name Type Description VSS P Ground power pin IO0 IO IO Port Pin 0 IO1 IO IO Port Pin 1 IO2 IO ...

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Schematic Figure 1-1. Typical Circuit Vunreg Voltage Reg IO Port pins Change Note: The central pad on the underside of the chip is a Vss pin and should be connected to ground. Note: Suggested regulator manufacturers: • Torex (XC6215 ...

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Overview 2.1 Introduction The AT42QT1060 (QT1060 digital burst mode charge-transfer (QT driver designed specifically for mobile phone applications. The device can sense from two to six keys four keys can be disabled by not installing ...

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... Adjacent Key Suppression (AKS) Technology The device includes Atmel’s patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. AT42QT1060 6 Section 6 ...

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There can be one AKS group, implemented so that only one key in the group may be reported as being touched at any one time. A key with a higher delta signal dominates and pushes a key with a smaller ...

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Calibration The command byte can force a recalibration at any time by writing a nonzero value to the calibration byte. This can be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection. When ...

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... Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency interference (RFI). For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouch Touch Technology area of Atmel’s website, www.atmel.com. 9505E–AT42–02/09 Section 6.20 on page Section 6 ...

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LED Traces and Other Switching Signals Digital switching signals near the sense lines induce transients into the acquired signals, deteriorating the SNR performance of the device. Such signals should be routed away from the sensing traces and electrodes, or ...

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I C-compatible Bus Operation 4.1 Interface Bus More detailed information about the www.i2C-bus.org. Devices are connected onto the Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all devices must be open-drain type. ...

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Figure 4-3. 4.3 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between ...

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Data Packet Format All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the Receiver is responsible ...

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I C-compatible Communications 2 5.1 I C-compatible Protocol 5.1.1 Protocol 2 The I C-compatible protocol is based around access to an address table (see page 17) and supports multibyte reads and writes. The maximum clock rate is 100 ...

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Table 5-1. Key MemAddress Data P 1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ...

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The device resets the internal address to the location indicated by the memory address sent to it previously. Therefore, there is no need to send the memory address again when reading from the same location. 5.4 SDA, SCL 2 ...

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Setups 6.1 Introduction The device calibrates and processes signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these algorithms to suit each ...

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Table 6-1. Internal Register Address Allocation (Continued) Address Use R/W 40 – 51 Key 0 – 5 Signal 52 – 63 Key 0 – 5 Reference Note: Res'd = Reserved; only write zero to these bits. 6.2 Address 0: Chip ...

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Address 5: Input Port Status Table 6-6. Address 5 INPUT 0 – 6: these bits indicate the state of the IO lines that are configured as inputs; indicating logic 1 on the input, 0 indicating logic 0. The bits ...

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Address 15: Positive Recalibration Delay Table 6-10. Address 15 POSITIVE RECALIBRATION DELAY: If any key is found to have a significant drop in capacitance, i.e. an “away from touch” signal, then this is deemed error condition. ...

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LP7 – ...254 255 A value of zero causes the device to enter SLEEP mode where no measurements are performed. A value of 255 causes the device to enter Free-run mode where measurements are ...

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Address 25: AKS Mask Table 6-15. Address 25 KEY0 – 5 (AKS Mask): these bits control which keys are included in the AKS group. A the corresponding key is included in the AKS group and may only go into ...

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Address 29: User Output Buffer Table 6-19. Address 29 IO0 – 6 (User Output Buffer): these bits control the output level for the IO's that are configured as outputs. A inactive. See Default: 0 (all IO's inactive) 6.20 Address ...

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Address 52 63: Reference Data – Table 6-23. Address – 63 REFERENCE DATA: addresses 52 – 63 allow reference data to be read for each key, starting with key 0. There are two bytes of data ...

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Setting Up Procedures To Set Up Keys Set the number of keys required by leaving the SNS pins unconnected in unused keys. Determine whether a change in the corresponding bit in the detection status register generates a transition on ...

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Specifications 8.1 Absolute Maximum Specifications Vdd Max continuous pin current, any control or drive pin Short circuit duration to ground, any pin Short circuit duration to Vdd, any pin Voltage forced onto any pin CAUTION: Stresses beyond those listed ...

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Cs = 10nF pF 10k LP Mode 0 (SLEEP) 1 (16 ms) 2 (32 ms) 4 (64 ms) 8 (128 ms) 16 (256 ms) 32 (512 ms) 64 (1024 ms) 8.4 AC Specifications Parameter Description ...

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Mechanical Dimensions Note Pin TOP VIEW 0.20 b BOTTOM VIEW The terminal # Laser-marked Feature. Note: 2325 Orchard Parkway San Jose, CA 95131 R AT42QT1060 28 The ...

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Marking There are two possible types of chip marking. Pin 1 ID Abbreviation of Part number; AT 42QT Part number; AT42QT1060-MMU 8.7 Part Number Part Number AT42QT1060-MMU 8.8 Moisture Sensitivity Level (MSL) 9505E–AT42–02/ LTCODE 1060 1060 -MMU ...

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Revision History Revision Number Revision A – September 2008 Revision B – October 2008 Revision C – November 2008 Revision D – December 2008 Revision E – February 2009 AT42QT1060 30 History  Initial Release for code revision 3.0  ...

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Notes 9505E–AT42–02/09 AT42QT1060 31 ...

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... LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’ ...