DK-N2EVAL-3C25N Altera, DK-N2EVAL-3C25N Datasheet - Page 30

KIT DEV NIOS II CYCLONE III ED.

DK-N2EVAL-3C25N

Manufacturer Part Number
DK-N2EVAL-3C25N
Description
KIT DEV NIOS II CYCLONE III ED.
Manufacturer
Altera
Series
Cyclone® IIIr
Type
FPGAr
Datasheets

Specifications of DK-N2EVAL-3C25N

Contents
Development Board, Module, and Software
Silicon Manufacturer
Altera
Core Architecture
FPGA
Core Sub-architecture
Cyclone
Silicon Core Number
EP3C
Silicon Family Name
Cyclone III
Rohs Compliant
Yes
For Use With/related Products
EP3C25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-2411
DK-N2EVAL-3C25N-OB
DK-NIOSEVAL-3C25N
NEEK

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DK-N2EVAL-3C25N
Manufacturer:
ALTERA
0
Devices
Cyclone IV GX FPGA Features
1
2
3
28
Maximum LVDS channels, transceiver channels, PLLs, and PCIe hard IP blocks for the product line shown. Various packages offer a variety options to meet your design needs.
Transceiver performance varies by product line and package offering.
EP4CGX30 supports 3.125 Gbps only in F484 package option.
LEs
M9K memory blocks
Embedded memory (Kb)
18-bit x 18-bit multipliers
Speed grades
(fastest to slowest)
Global clock networks
PLLs/unique outputs
Configuration file size (Mb)
I/O voltage levels
supported (V)
I/O standards supported
Emulated LVDS channels
LVDS channels, 840 Mbps
(receive/transmit)
Transceiver (SERDES)
channels (2.5/3.125 Gbps)
PCIe hard IP blocks
Gen1
Memory devices supported
Altera Product Catalog
2011
EP4CGX15
www.altera.com
-6,-7,-8
14,400
3/15
540
2/0
3.8
7/7
60
20
LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15, Differential SSTL-18,
Differential SSTL-2, Differential HSTL-12, Differential HSTL-15, Differential HSTL-18, SSTL-15 (I and II),
0
9
SSTL-18 (I and II), SSTL-2 (I and II), 1.2-V HSTL (I and II), 1.5-V HSTL (I and II), 1.8-V HSTL (I and II)
EP4CGX22
-6,-7,-8
21,280
14/14
4/20
756
2/0,
7.6
4/0
84
40
20
40
Cyclone IV GX FPGAs (1.2 V)
EP4CGX30
-6,-7,-8
29,440
1,080
14/14
4/20
120
4/0,
0/4
7.6
DDR2, DDR, QDR II, RLDRAM II, SDR
80
20
40
See supported protocols and data rates on page 63
3
1.2, 1.5, 1.8, 2.5, 3.3
EP4CGX50
-6,-7,-8
49,888
2,502
49/49
8/40
24.5
278
140
0/8
30
73
1
1
, 3.125-Gbps Transceivers
EP4CGX75
-6,-7,-8
73,920
4,158
49/49
8/40
24.5
462
198
0/8
30
73
EP4CGX110
109,424
5,490
59/59
2
-7,-8
8/40
47.6
666
280
139
0/8
30
EP4CGX150
149,760
6,480
59/59
-7,-8
8/40
47.6
720
360
139
0/8
30

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