KIT908E625DWBEVB Freescale Semiconductor, KIT908E625DWBEVB Datasheet - Page 19

• Manufacturer Part Number: KIT908E625DWBEVB
• Description: KIT EVAL PRELIM MM98E625/26
• Manufacturer: Freescale Semiconductor

Specifications of KIT908E625DWBEVB

• Processor To Be Evaluated: MM908E625
• Data Bus Width: 16 bit
• Interface Type: SPI
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SERIAL SPI INTERFACE
•
• MOSI—Master-Out Slave-In
prepared. The falling edge on the
of a new data transfer and puts MISO in the low-impedance
mode. The first valid data are moved to MISO with the rising
edge of SPSCK.
SPSCK. The MOSI input is sampled on a falling edge of
SPSCK. The data transfer is only valid if exactly 16 sample
clock edges are present in the active phase of
the register by the rising edge of
internally latched into the SPI at the time when the parity bit
is transferred.
A4:A0
R/
Analog Integrated Circuit Device Data
Freescale Semiconductor
SPSCK
MOSI
MISO
The SPI creates the communication link between the
microcontroller and the 908E625.
The interface consists of four pins. See
SS
During the inactive phase of
The MISO output changes data on a rising edge of
After a write operation, the transmitted data is latched into
Contains the address of the desired register.
Contains information about a read or a write operation.
• If R/
• If R/
W
SS
information, slave just transmits back register data.
second byte, slave sends concurrently contents of
—Slave Select
Rising edge of SPSCK
Change MISO/MOSI
W
W
= 1, the second byte of master contains no valid
= 0, the master sends data to be written in the
SS
HIGH forces MISO to high impedance.
Output
R/W
S7
Falling edge of SPSCK
Sample MISO/MOSI
Input
A4
S6
SS
SS
SS
Read/Write, Address, Parity
, the new data transfer is
A3
S5
System Status Register
. Register read data is
line indicates the start
A2
S4
Figure
A1
S3
SS
9:
.
A0
S2
Figure 9. SPI Protocol
Slave latch
register address
S1
P
S0
X
• MISO—Master-In Slave-Out
• SPSCK—Serial Clock
The master sends address and data, slave system status,
and data of the selected address.
PARITY P
number contained within R/
is odd, P equals 1. For example, if R/
then P equals 0.
BIT X
MASTER DATA BYTE
operation.
SLAVE STATUS BYTE
independent of whether it is a write or read operation or which
register was selected.
A complete data transfer via the SPI consists of 2 bytes.
The parity bit is equal to 0 if the number of 1 bits is an even
The parity bit is only evaluated during a write operation.
Not used.
Contains data to be written or no valid data during a read
Contains the contents of the System Status Register ($0c)
selected register prior to write operation, write data is
latched in the SMARTMOS
SS
.
D7
D7
D6
D6
D5
D5
Data (Register write)
Data (Register read)
FUNCTIONAL DEVICE OPERATION
D4
D4
W
, A4:A0. If the number of 1 bits
D3
D3
™
register on rising edge of
D2
D2
W
OPERATIONAL MODES
= 1, A4:A0 = 00001,
D1
D1
D0
D0
Slave latch
data
908E625
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